Lines Matching refs:rd
51 bool Arm32Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED, in ShifterOperandCanHold()
59 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, in and_() argument
61 EmitType01(cond, so.type(), AND, 0, rn, rd, so); in and_()
65 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, in eor() argument
67 EmitType01(cond, so.type(), EOR, 0, rn, rd, so); in eor()
71 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, in sub() argument
73 EmitType01(cond, so.type(), SUB, 0, rn, rd, so); in sub()
76 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, in rsb() argument
78 EmitType01(cond, so.type(), RSB, 0, rn, rd, so); in rsb()
81 void Arm32Assembler::rsbs(Register rd, Register rn, const ShifterOperand& so, in rsbs() argument
83 EmitType01(cond, so.type(), RSB, 1, rn, rd, so); in rsbs()
87 void Arm32Assembler::add(Register rd, Register rn, const ShifterOperand& so, in add() argument
89 EmitType01(cond, so.type(), ADD, 0, rn, rd, so); in add()
93 void Arm32Assembler::adds(Register rd, Register rn, const ShifterOperand& so, in adds() argument
95 EmitType01(cond, so.type(), ADD, 1, rn, rd, so); in adds()
99 void Arm32Assembler::subs(Register rd, Register rn, const ShifterOperand& so, in subs() argument
101 EmitType01(cond, so.type(), SUB, 1, rn, rd, so); in subs()
105 void Arm32Assembler::adc(Register rd, Register rn, const ShifterOperand& so, in adc() argument
107 EmitType01(cond, so.type(), ADC, 0, rn, rd, so); in adc()
111 void Arm32Assembler::sbc(Register rd, Register rn, const ShifterOperand& so, in sbc() argument
113 EmitType01(cond, so.type(), SBC, 0, rn, rd, so); in sbc()
117 void Arm32Assembler::rsc(Register rd, Register rn, const ShifterOperand& so, in rsc() argument
119 EmitType01(cond, so.type(), RSC, 0, rn, rd, so); in rsc()
145 void Arm32Assembler::orr(Register rd, Register rn, in orr() argument
147 EmitType01(cond, so.type(), ORR, 0, rn, rd, so); in orr()
151 void Arm32Assembler::orrs(Register rd, Register rn, in orrs() argument
153 EmitType01(cond, so.type(), ORR, 1, rn, rd, so); in orrs()
157 void Arm32Assembler::mov(Register rd, const ShifterOperand& so, Condition cond) { in mov() argument
158 EmitType01(cond, so.type(), MOV, 0, R0, rd, so); in mov()
162 void Arm32Assembler::movs(Register rd, const ShifterOperand& so, Condition cond) { in movs() argument
163 EmitType01(cond, so.type(), MOV, 1, R0, rd, so); in movs()
167 void Arm32Assembler::bic(Register rd, Register rn, const ShifterOperand& so, in bic() argument
169 EmitType01(cond, so.type(), BIC, 0, rn, rd, so); in bic()
173 void Arm32Assembler::mvn(Register rd, const ShifterOperand& so, Condition cond) { in mvn() argument
174 EmitType01(cond, so.type(), MVN, 0, R0, rd, so); in mvn()
178 void Arm32Assembler::mvns(Register rd, const ShifterOperand& so, Condition cond) { in mvns() argument
179 EmitType01(cond, so.type(), MVN, 1, R0, rd, so); in mvns()
183 void Arm32Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { in mul() argument
185 EmitMulOp(cond, 0, R0, rd, rn, rm); in mul()
189 void Arm32Assembler::mla(Register rd, Register rn, Register rm, Register ra, in mla() argument
192 EmitMulOp(cond, B21, ra, rd, rn, rm); in mla()
196 void Arm32Assembler::mls(Register rd, Register rn, Register rm, Register ra, in mls() argument
199 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm); in mls()
210 void Arm32Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) { in sdiv() argument
211 CHECK_NE(rd, kNoRegister); in sdiv()
219 (static_cast<int32_t>(rd) << 16) | in sdiv()
226 void Arm32Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) { in udiv() argument
227 CHECK_NE(rd, kNoRegister); in udiv()
235 (static_cast<int32_t>(rd) << 16) | in udiv()
242 void Arm32Assembler::sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) { in sbfx() argument
243 CHECK_NE(rd, kNoRegister); in sbfx()
253 (static_cast<uint32_t>(rd) << 12) | in sbfx()
261 void Arm32Assembler::ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) { in ubfx() argument
262 CHECK_NE(rd, kNoRegister); in ubfx()
272 (static_cast<uint32_t>(rd) << 12) | in ubfx()
280 void Arm32Assembler::ldr(Register rd, const Address& ad, Condition cond) { in ldr() argument
281 EmitMemOp(cond, true, false, rd, ad); in ldr()
285 void Arm32Assembler::str(Register rd, const Address& ad, Condition cond) { in str() argument
286 EmitMemOp(cond, false, false, rd, ad); in str()
290 void Arm32Assembler::ldrb(Register rd, const Address& ad, Condition cond) { in ldrb() argument
291 EmitMemOp(cond, true, true, rd, ad); in ldrb()
295 void Arm32Assembler::strb(Register rd, const Address& ad, Condition cond) { in strb() argument
296 EmitMemOp(cond, false, true, rd, ad); in strb()
300 void Arm32Assembler::ldrh(Register rd, const Address& ad, Condition cond) { in ldrh() argument
301 EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad); in ldrh()
305 void Arm32Assembler::strh(Register rd, const Address& ad, Condition cond) { in strh() argument
306 EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad); in strh()
310 void Arm32Assembler::ldrsb(Register rd, const Address& ad, Condition cond) { in ldrsb() argument
311 EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad); in ldrsb()
315 void Arm32Assembler::ldrsh(Register rd, const Address& ad, Condition cond) { in ldrsh() argument
316 EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad); in ldrsh()
320 void Arm32Assembler::ldrd(Register rd, const Address& ad, Condition cond) { in ldrd() argument
321 CHECK_EQ(rd % 2, 0); in ldrd()
322 EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, ad); in ldrd()
326 void Arm32Assembler::strd(Register rd, const Address& ad, Condition cond) { in strd() argument
327 CHECK_EQ(rd % 2, 0); in strd()
328 EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, ad); in strd()
588 Register rd, in EmitType01() argument
590 CHECK_NE(rd, kNoRegister); in EmitType01()
597 static_cast<int32_t>(rd) << kRdShift | in EmitType01()
615 Register rd, in EmitMemOp() argument
617 CHECK_NE(rd, kNoRegister); in EmitMemOp()
635 (static_cast<int32_t>(rd) << kRdShift) | in EmitMemOp()
644 (static_cast<int32_t>(rd) << kRdShift) | in EmitMemOp()
653 Register rd, in EmitMemOpAddressMode3() argument
655 CHECK_NE(rd, kNoRegister); in EmitMemOpAddressMode3()
661 (static_cast<int32_t>(rd) << kRdShift) | in EmitMemOpAddressMode3()
686 Register rd, in EmitShiftImmediate() argument
693 static_cast<int32_t>(rd) << kRdShift | in EmitShiftImmediate()
703 Register rd, in EmitShiftRegister() argument
710 static_cast<int32_t>(rd) << kRdShift | in EmitShiftRegister()
731 void Arm32Assembler::clz(Register rd, Register rm, Condition cond) { in clz() argument
732 CHECK_NE(rd, kNoRegister); in clz()
735 CHECK_NE(rd, PC); in clz()
739 (static_cast<int32_t>(rd) << kRdShift) | in clz()
745 void Arm32Assembler::movw(Register rd, uint16_t imm16, Condition cond) { in movw() argument
749 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); in movw()
754 void Arm32Assembler::movt(Register rd, uint16_t imm16, Condition cond) { in movt() argument
758 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); in movt()
764 Register rd, Register rn, in EmitMulOp() argument
766 CHECK_NE(rd, kNoRegister); in EmitMulOp()
774 (static_cast<int32_t>(rd) << kRdShift) | in EmitMulOp()
816 void Arm32Assembler::strex(Register rd, in strex() argument
821 CHECK_NE(rd, kNoRegister); in strex()
828 (static_cast<int32_t>(rd) << kStrExRdShift) | in strex()
834 void Arm32Assembler::strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) { in strexd() argument
835 CHECK_NE(rd, kNoRegister); in strexd()
840 CHECK_NE(rd, rt); in strexd()
841 CHECK_NE(rd, rt2); in strexd()
850 static_cast<uint32_t>(rd) << 12 | in strexd()
1153 void Arm32Assembler::Lsl(Register rd, Register rm, uint32_t shift_imm, in Lsl() argument
1157 movs(rd, ShifterOperand(rm, LSL, shift_imm), cond); in Lsl()
1159 mov(rd, ShifterOperand(rm, LSL, shift_imm), cond); in Lsl()
1164 void Arm32Assembler::Lsr(Register rd, Register rm, uint32_t shift_imm, in Lsr() argument
1169 movs(rd, ShifterOperand(rm, LSR, shift_imm), cond); in Lsr()
1171 mov(rd, ShifterOperand(rm, LSR, shift_imm), cond); in Lsr()
1176 void Arm32Assembler::Asr(Register rd, Register rm, uint32_t shift_imm, in Asr() argument
1181 movs(rd, ShifterOperand(rm, ASR, shift_imm), cond); in Asr()
1183 mov(rd, ShifterOperand(rm, ASR, shift_imm), cond); in Asr()
1188 void Arm32Assembler::Ror(Register rd, Register rm, uint32_t shift_imm, in Ror() argument
1192 movs(rd, ShifterOperand(rm, ROR, shift_imm), cond); in Ror()
1194 mov(rd, ShifterOperand(rm, ROR, shift_imm), cond); in Ror()
1198 void Arm32Assembler::Rrx(Register rd, Register rm, bool setcc, Condition cond) { in Rrx() argument
1200 movs(rd, ShifterOperand(rm, ROR, 0), cond); in Rrx()
1202 mov(rd, ShifterOperand(rm, ROR, 0), cond); in Rrx()
1207 void Arm32Assembler::Lsl(Register rd, Register rm, Register rn, in Lsl() argument
1210 movs(rd, ShifterOperand(rm, LSL, rn), cond); in Lsl()
1212 mov(rd, ShifterOperand(rm, LSL, rn), cond); in Lsl()
1217 void Arm32Assembler::Lsr(Register rd, Register rm, Register rn, in Lsr() argument
1220 movs(rd, ShifterOperand(rm, LSR, rn), cond); in Lsr()
1222 mov(rd, ShifterOperand(rm, LSR, rn), cond); in Lsr()
1227 void Arm32Assembler::Asr(Register rd, Register rm, Register rn, in Asr() argument
1230 movs(rd, ShifterOperand(rm, ASR, rn), cond); in Asr()
1232 mov(rd, ShifterOperand(rm, ASR, rn), cond); in Asr()
1237 void Arm32Assembler::Ror(Register rd, Register rm, Register rn, in Ror() argument
1240 movs(rd, ShifterOperand(rm, ROR, rn), cond); in Ror()
1242 mov(rd, ShifterOperand(rm, ROR, rn), cond); in Ror()
1290 void Arm32Assembler::Push(Register rd, Condition cond) { in Push() argument
1291 str(rd, Address(SP, -kRegisterSize, Address::PreIndex), cond); in Push()
1295 void Arm32Assembler::Pop(Register rd, Condition cond) { in Pop() argument
1296 ldr(rd, Address(SP, kRegisterSize, Address::PostIndex), cond); in Pop()
1310 void Arm32Assembler::Mov(Register rd, Register rm, Condition cond) { in Mov() argument
1311 if (rd != rm) { in Mov()
1312 mov(rd, ShifterOperand(rm), cond); in Mov()
1350 void Arm32Assembler::AddConstant(Register rd, int32_t value, Condition cond) { in AddConstant() argument
1351 AddConstant(rd, rd, value, cond); in AddConstant()
1355 void Arm32Assembler::AddConstant(Register rd, Register rn, int32_t value, in AddConstant() argument
1358 if (rd != rn) { in AddConstant()
1359 mov(rd, ShifterOperand(rn), cond); in AddConstant()
1368 add(rd, rn, shifter_op, cond); in AddConstant()
1370 sub(rd, rn, shifter_op, cond); in AddConstant()
1375 add(rd, rn, ShifterOperand(IP), cond); in AddConstant()
1378 sub(rd, rn, ShifterOperand(IP), cond); in AddConstant()
1385 add(rd, rn, ShifterOperand(IP), cond); in AddConstant()
1391 void Arm32Assembler::AddConstantSetFlags(Register rd, Register rn, int32_t value, in AddConstantSetFlags() argument
1395 adds(rd, rn, shifter_op, cond); in AddConstantSetFlags()
1397 subs(rd, rn, shifter_op, cond); in AddConstantSetFlags()
1402 adds(rd, rn, ShifterOperand(IP), cond); in AddConstantSetFlags()
1405 subs(rd, rn, ShifterOperand(IP), cond); in AddConstantSetFlags()
1412 adds(rd, rn, ShifterOperand(IP), cond); in AddConstantSetFlags()
1417 void Arm32Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) { in LoadImmediate() argument
1420 mov(rd, shifter_op, cond); in LoadImmediate()
1422 mvn(rd, shifter_op, cond); in LoadImmediate()
1424 movw(rd, Low16Bits(value), cond); in LoadImmediate()
1427 movt(rd, value_high, cond); in LoadImmediate()