Lines Matching refs:rd

55   void Add(GpuRegister rd, GpuRegister rs, GpuRegister rt);
57   void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
59   void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
61   void Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt);
62   void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
63   void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64
69   void MulR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
70   void DivR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
71   void ModR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
72   void DivuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
73   void ModuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R2
74   void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
75   void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
76   void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
77   void DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
78   void ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // R6
79   void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
80   void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
81   void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
82   void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
83   void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt);  // MIPS64 R6
85   void And(GpuRegister rd, GpuRegister rs, GpuRegister rt);
87   void Or(GpuRegister rd, GpuRegister rs, GpuRegister rt);
89   void Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
91   void Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
93   void Seb(GpuRegister rd, GpuRegister rt);  // R2+
94   void Seh(GpuRegister rd, GpuRegister rt);  // R2+
97   void Sll(GpuRegister rd, GpuRegister rt, int shamt);
98   void Srl(GpuRegister rd, GpuRegister rt, int shamt);
99   void Sra(GpuRegister rd, GpuRegister rt, int shamt);
100   void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
101   void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
102   void Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs);
103   void Dsll(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
104   void Dsrl(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
105   void Dsra(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
106   void Dsll32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
107   void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
108   void Dsra32(GpuRegister rd, GpuRegister rt, int shamt);  // MIPS64
109   void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
110   void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
111   void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs);  // MIPS64
124   void Mfhi(GpuRegister rd);  // R2
125   void Mflo(GpuRegister rd);  // R2
132   void Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt);
133   void Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
141   void Jalr(GpuRegister rd, GpuRegister rs);
189   void Move(GpuRegister rd, GpuRegister rs);
190   void Clear(GpuRegister rd);
191   void Not(GpuRegister rd, GpuRegister rs);
194   void LoadConst32(GpuRegister rd, int32_t value);
195   void LoadConst64(GpuRegister rd, int64_t value);  // MIPS64
344   void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct);