Lines Matching refs:D

8 (W), PGP key ID and fingerprint (P), description (D), snail-mail address
15 D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
19 D: LCSSA pass and related LoopUnswitch work
20 D: GVNPRE pass, DataLayout refactoring, random improvements
23 D: MingW Win32 API portability layer
27 D: __declspec attributes, Windows support, general bug fixing
31 D: PowerPC backend developer
32 D: Target-independent code generator and analysis improvements
36 D: ET-Forest implementation.
37 D: Sparse bitmap
41 D: General bug fixing/fit & finish, mostly in Clang
45 D: APFloat implementation.
50 D: Portions of X86 and Sparc JIT compilers, PowerPC backend
51 D: Incremental bitcode loader
55 D: The `mem2reg' pass - promotes values stored in memory to registers
59 D: Loop unrolling with run-time trip counts.
64 D: Hashing algorithms and interfaces
65 D: Inline cost analysis
66 D: Machine block placement pass
67 D: SROA
71 D: Fixes to the Reassociation pass, various improvement patches
75 D: ARM and X86 backends
76 D: Instruction scheduler improvements
77 D: Register allocator improvements
78 D: Loop optimizer improvements
79 D: Target-independent code generator improvements
85 D: LLVM Makefile improvements
86 D: Clang diagnostic & driver tweaks
92 D: Native Win32 API portability layer
96 D: Original Autoconf support, documentation improvements, bug fixes
100 D: Deterministic finite automaton based infrastructure for VLIW packetization
104 D: Bug fixes and minor improvements
108 D: The ARM backend
112 D: AArch64 machine description for Cortex-A53
116 D: Linear scan register allocator, many codegen improvements, Java frontend
120 D: Basic-block autovectorization, PowerPC backend improvements
124 D: LIT patches and documentation.
128 D: Miscellaneous bug fixes
133 D: Portions of X86 static and JIT compilers; initial SparcV8 backend
134 D: Dynamic trace optimizer
135 D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
140 D: PPC backend fixes for Linux
144 D: Portions of the PowerPC backend
148 D: Callgraph class cleanups
152 D: Author of llvmc2
156 D: Miscellaneous bug fixes
160 D: Thumb-2 code generator
164 D: Miscellaneous bug fixes
165 D: Register allocation refactoring
169 D: Improvements for space efficiency
174 D: SjLj exception handling support
175 D: General fixes and improvements for the ARM back-end
176 D: MCJIT
177 D: ARM integrated assembler and assembly parser
178 D: Led effort for the backend formerly known as ARM64
182 D: PBQP-based register allocator
186 D: Pluggable GC support
187 D: C interface
188 D: Ocaml bindings
192 D: JIT support for ARM
196 D: Visual C++ compatibility fixes
200 D: Nightly Tester
204 D: ARM constant islands improvements
205 D: Tail merging improvements
206 D: Rewrite X87 back end
207 D: Use APFloat for floating point constants widely throughout compiler
208 D: Implement X87 long double
212 D: Support for packed types
216 D: Author of LLVM Ada bindings
220 D: llvm-config script
224 D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
225 D: x86/linux PIC codegen, aliases, regparm/visibility attributes
226 D: Switch lowering refactoring
230 D: Author of the original C backend
234 D: Miscellaneous bug fixes
238 D: Implemented DFA-based target independent VLIW packetizer
242 D: aligned load/store support, parts of noalias and restrict support
243 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
244 D: address spaces
248 D: Improvements to the PPC backend, instruction scheduling
249 D: Debug and Dwarf implementation
250 D: Auto upgrade mangler
251 D: llvm-gcc4 svn wrangler
256 D: Primary architect of LLVM
261 D: The initial llvm-ar tool, converted regression testsuite to dejagnu
262 D: Modulo scheduling in the SparcV9 backend
263 D: Release manager (1.7+)
269 D: Debian and Ubuntu packaging
270 D: Continuous integration with jenkins
275 D: Alpha backend
276 D: Sampling based profiling
280 D: PredicateSimplifier pass
284 D: Backend for Qualcomm's Hexagon VLIW processor.
290 D: Mips backend
291 D: Random ARM integrated assembler and assembly parser improvements
292 D: General X86 AVX1 support
297 D: IA64 backend, BigBlock register allocator
301 D: Clang semantic analysis and IR generation
305 D: Line number support for llvmgcc
309 D: Test suite fixes for FreeBSD
313 D: Added STI Cell SPU backend.
317 D: Support for implicit TLS model used with MS VC runtime
318 D: Dumping of Win64 EH structures
323 D: Cygwin and MinGW support.
324 D: Win32 tweaks.
330 D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
331 D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
332 D: and error clean ups.
336 D: Visual C++ compatibility fixes
340 D: Machine code verifier
341 D: Blackfin backend
342 D: Fast register allocator
343 D: Greedy register allocator
347 D: XCore backend
351 D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
352 D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
353 D: Optimizer improvements, Loop Index Split
357 D: Fixes and improvements to the AArch64 backend
362 D: MicroBlaze backend
366 D: MSVC support
371 D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
375 D: Some bugfixes to CellSPU
379 D: Cmake dependency chain and various bug fixes
384 D: ARM calling conventions rewrite, hard float support
389 D: AArch64 fast instruction selection pass
390 D: Fixes and improvements to the ARM fast-isel pass
391 D: Fixes and improvements to the AArch64 backend
395 D: X86 code generation improvements, Loop Vectorizer.
399 D: MSIL backend
404 D: Ada support in llvm-gcc
405 D: Dragonegg plugin
406 D: Exception handling improvements
407 D: Type legalizer rewrite
411 D: Graph coloring register allocator for the Sparc64 backend
415 D: Tail call optimization for the x86 backend
419 D: Miscellaneous bug fixes
423 D: The `paths' pass
427 D: Shepherding Windows COFF support into MC.
428 D: Lots of Windows stuff.
433 D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
438 D: C++ frontend next generation standards implementation
442 D: X86 codegen and disassembler improvements. AVX2 support.
446 D: Miscellaneous bug fixes
450 D: C++ bugs filed, and C++ front-end bug fixes.
454 D: ARM backend improvements
455 D: Thread Local Storage implementation
460 D: Release manager, IR Linker, LTO
461 D: Bunches of stuff
465 D: Advanced SIMD (NEON) support in the ARM backend.