Lines Matching refs:SRL
1059 else if (Opc == ISD::SRL) in PromoteIntShiftOp()
1329 case ISD::SRL: return visitSRL(N); in visit()
1422 case ISD::SRL: in combine()
2142 SDValue SRL = in visitSDIV() local
2143 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN, in visitSDIV()
2146 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL); in visitSDIV()
2147 AddToWorklist(SRL.getNode()); in visitSDIV()
2195 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, in visitUDIV()
2209 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add); in visitUDIV()
2353 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHS()
2389 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, in visitMULHU()
2467 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitSMUL_LOHI()
2497 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, in visitUMUL_LOHI()
2587 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || in SimplifyBinOpWithSameOpcodeHands()
2768 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && in visitANDLike()
3129 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) in MatchBSwapHWordLow()
3153 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) in MatchBSwapHWordLow()
3155 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) in MatchBSwapHWordLow()
3214 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res, in MatchBSwapHWordLow()
3230 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) in isBSwapHWordElement()
3253 if (N0.getOpcode() != ISD::SRL) in isBSwapHWordElement()
3365 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt)); in MatchBSwapHWord()
3622 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { in MatchRotateHalf()
4071 BinOpLHSVal->getOpcode() != ISD::SRL) || in visitShiftByConstant()
4246 N0.getOperand(0).getOpcode() == ISD::SRL) { in visitSHL()
4268 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in visitSHL()
4281 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), in visitSHL()
4406 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT, in visitSRA()
4427 (N0.getOperand(0).getOpcode() == ISD::SRL || in visitSRA()
4455 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1); in visitSRA()
4484 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); in visitSRL()
4500 if (N1C && N0.getOpcode() == ISD::SRL) { in visitSRL()
4506 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), in visitSRL()
4513 N0.getOperand(0).getOpcode() == ISD::SRL && in visitSRL()
4526 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT, in visitSRL()
4550 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
4552 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT, in visitSRL()
4567 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1); in visitSRL()
4595 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op, in visitSRL()
4610 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1); in visitSRL()
6036 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && in visitZERO_EXTEND()
6240 case ISD::SRL: in GetDemandedBits()
6253 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(), in GetDemandedBits()
6282 } else if (Opc == ISD::SRL) { in ReduceLoadWidth()
6302 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { in ReduceLoadWidth()
6481 if (N0.getOpcode() == ISD::SRL) { in visitSIGN_EXTEND_INREG()
6901 X = DAG.getNode(ISD::SRL, SDLoc(X), in visitBITCAST()
8399 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || in visitBRCOND()
8402 N1.getOperand(0).getOpcode() == ISD::SRL))) { in visitBRCOND()
9585 if (User->getOpcode() == ISD::SRL && User->hasOneUse() && in SliceUpLoad()
9754 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal, in ShrinkLoadReplaceStoreWithStore()
12772 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), in SimplifySelectCC()
12894 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, in SimplifySelectCC()
12903 return DAG.getNode(ISD::SRL, DL, XType, in SimplifySelectCC()
12910 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0, in SimplifySelectCC()