405       unsigned Op1 = getRegForValue(I->getOperand(1));  in selectBinaryOp()  local
406       if (!Op1)  in selectBinaryOp()
411           fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill,  in selectBinaryOp()
465   unsigned Op1 = getRegForValue(I->getOperand(1));  in selectBinaryOp()  local
466   if (!Op1) // Unhandled operand. Halt "fast" selection and bail.  in selectBinaryOp()
472                                    ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);  in selectBinaryOp()
1742                                    bool Op0IsKill, unsigned Op1,  in fastEmitInst_rr()  argument
1748   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);  in fastEmitInst_rr()
1753         .addReg(Op1, getKillRegState(Op1IsKill));  in fastEmitInst_rr()
1757         .addReg(Op1, getKillRegState(Op1IsKill));  in fastEmitInst_rr()
1766                                     bool Op0IsKill, unsigned Op1,  in fastEmitInst_rrr()  argument
1773   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);  in fastEmitInst_rrr()
1779         .addReg(Op1, getKillRegState(Op1IsKill))  in fastEmitInst_rrr()
1784         .addReg(Op1, getKillRegState(Op1IsKill))  in fastEmitInst_rrr()
1863                                     bool Op0IsKill, unsigned Op1,  in fastEmitInst_rri()  argument
1869   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);  in fastEmitInst_rri()
1874         .addReg(Op1, getKillRegState(Op1IsKill))  in fastEmitInst_rri()
1879         .addReg(Op1, getKillRegState(Op1IsKill))  in fastEmitInst_rri()
1889                                      unsigned Op0, bool Op0IsKill, unsigned Op1,  in fastEmitInst_rrii()  argument
1896   Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);  in fastEmitInst_rrii()
1901         .addReg(Op1, getKillRegState(Op1IsKill))  in fastEmitInst_rrii()
1907         .addReg(Op1, getKillRegState(Op1IsKill))  in fastEmitInst_rrii()