Lines Matching refs:SrcVT
153 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
188 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
219 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
223 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
227 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1107 MVT SrcVT = RetVT; in emitAddSub() local
1134 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1225 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2320 MVT SrcVT; in selectBranch() local
2322 isTypeSupported(TI->getOperand(0)->getType(), SrcVT)) { in selectBranch()
2329 if (SrcVT == MVT::i64) { in selectBranch()
2751 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true); in selectFPToInt() local
2752 if (SrcVT == MVT::f128) in selectFPToInt()
2756 if (SrcVT == MVT::f64) { in selectFPToInt()
2787 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true); in selectIntToFP() local
2790 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) { in selectIntToFP()
2792 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
2799 if (SrcVT == MVT::i64) { in selectIntToFP()
2958 MVT SrcVT = ArgVT; in processCallArgs() local
2959 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
2968 MVT SrcVT = ArgVT; in processCallArgs() local
2969 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
3762 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc() local
3765 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 && in selectTrunc()
3766 SrcVT != MVT::i8) in selectTrunc()
3783 if (SrcVT == MVT::i64) { in selectTrunc()
3915 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSL_ri() argument
3918 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
3920 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSL_ri()
3921 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSL_ri()
3929 unsigned SrcBits = SrcVT.getSizeInBits(); in emitLSL_ri()
3935 if (RetVT == SrcVT) { in emitLSL_ri()
3942 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
3982 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSL_ri()
4022 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSR_ri() argument
4025 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
4027 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSR_ri()
4028 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSR_ri()
4036 unsigned SrcBits = SrcVT.getSizeInBits(); in emitLSR_ri()
4042 if (RetVT == SrcVT) { in emitLSR_ri()
4049 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4087 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4091 SrcVT = RetVT; in emitLSR_ri()
4092 SrcBits = SrcVT.getSizeInBits(); in emitLSR_ri()
4103 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSR_ri()
4143 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitASR_ri() argument
4146 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitASR_ri()
4148 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitASR_ri()
4149 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitASR_ri()
4157 unsigned SrcBits = SrcVT.getSizeInBits(); in emitASR_ri()
4163 if (RetVT == SrcVT) { in emitASR_ri()
4170 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4212 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitASR_ri()
4225 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
4235 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && in emitIntExt()
4236 (SrcVT != MVT::i16) && (SrcVT != MVT::i32))) in emitIntExt()
4242 switch (SrcVT.SimpleTy) { in emitIntExt()
4335 MVT SrcVT) { in optimizeIntExtLoad() argument
4363 if (RetVT != MVT::i64 || SrcVT > MVT::i32) { in optimizeIntExtLoad()
4391 MVT SrcVT; in selectIntExt() local
4395 if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT)) in selectIntExt()
4399 if (optimizeIntExtLoad(I, RetVT, SrcVT)) in selectIntExt()
4411 if (RetVT == MVT::i64 && SrcVT != MVT::i64) { in selectIntExt()
4433 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4505 MVT SrcVT = VT; in selectMul() local
4511 SrcVT = VT; in selectMul()
4520 SrcVT = VT; in selectMul()
4533 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4571 MVT SrcVT = RetVT; in selectShift() local
4578 SrcVT = TmpVT; in selectShift()
4587 SrcVT = TmpVT; in selectShift()
4602 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4605 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4608 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4650 MVT RetVT, SrcVT; in selectBitCast() local
4652 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT)) in selectBitCast()
4658 if (RetVT == MVT::f32 && SrcVT == MVT::i32) in selectBitCast()
4660 else if (RetVT == MVT::f64 && SrcVT == MVT::i64) in selectBitCast()
4662 else if (RetVT == MVT::i32 && SrcVT == MVT::f32) in selectBitCast()
4664 else if (RetVT == MVT::i64 && SrcVT == MVT::f64) in selectBitCast()