Lines Matching refs:latency

18   let LoadLatency = 4; // Optimistic load latency.
94 // Define scheduler read/write resources and latency on Cyclone.
180 // shortening its writer's latency.
229 // latency. However, general heuristics should not model the
237 // Rt latency is latency WriteIS + WriteLD.
262 // Address pre/post increment is a simple ALU op with one cycle latency.
294 // System instructions get an invalid latency because the latency of
304 // Define some longer latency vector op types for Cyclone.
547 // TODO: Add 64-bit variant with 19 cycle latency.
548 // TODO: Specialize FSQRT for longer latency.
628 // same latency, this is acceptable.