301     bool fixupImmediateBr(ImmBranch &Br);
302     bool fixupConditionalBr(ImmBranch &Br);
303     bool fixupUnconditionalBr(ImmBranch &Br);
1543 bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {  in fixupImmediateBr()  argument
1544   MachineInstr *MI = Br.MI;  in fixupImmediateBr()
1548   if (isBBInRange(MI, DestBB, Br.MaxDisp))  in fixupImmediateBr()
1551   if (!Br.isCond)  in fixupImmediateBr()
1552     return fixupUnconditionalBr(Br);  in fixupImmediateBr()
1553   return fixupConditionalBr(Br);  in fixupImmediateBr()
1561 ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {  in fixupUnconditionalBr()  argument
1562   MachineInstr *MI = Br.MI;  in fixupUnconditionalBr()
1568   Br.MaxDisp = (1 << 21) * 2;  in fixupUnconditionalBr()
1584 ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {  in fixupConditionalBr()  argument
1585   MachineInstr *MI = Br.MI;  in fixupConditionalBr()
1609         BMI->getOpcode() == Br.UncondBr) {  in fixupConditionalBr()
1618       if (isBBInRange(MI, NewDest, Br.MaxDisp)) {  in fixupConditionalBr()
1648   Br.MI = &MBB->back();  in fixupConditionalBr()
1651     BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB)  in fixupConditionalBr()
1654     BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);  in fixupConditionalBr()
1656   unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);  in fixupConditionalBr()
1657   ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));  in fixupConditionalBr()
1766     ImmBranch &Br = ImmBranches[i];  in optimizeThumb2Branches()  local
1767     unsigned Opcode = Br.MI->getOpcode();  in optimizeThumb2Branches()
1787       MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();  in optimizeThumb2Branches()
1788       if (isBBInRange(Br.MI, DestBB, MaxOffs)) {  in optimizeThumb2Branches()
1789         DEBUG(dbgs() << "Shrink branch: " << *Br.MI);  in optimizeThumb2Branches()
1790         Br.MI->setDesc(TII->get(NewOpc));  in optimizeThumb2Branches()
1791         MachineBasicBlock *MBB = Br.MI->getParent();  in optimizeThumb2Branches()
1799     Opcode = Br.MI->getOpcode();  in optimizeThumb2Branches()
1805     if (!Br.MI->killsRegister(ARM::CPSR))  in optimizeThumb2Branches()
1810     ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg);  in optimizeThumb2Branches()
1817     MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();  in optimizeThumb2Branches()
1820     unsigned BrOffset = getOffsetOf(Br.MI) + 4 - 2;  in optimizeThumb2Branches()
1823       MachineBasicBlock::iterator CmpMI = Br.MI;  in optimizeThumb2Branches()
1824       if (CmpMI != Br.MI->getParent()->begin()) {  in optimizeThumb2Branches()
1832             MachineBasicBlock *MBB = Br.MI->getParent();  in optimizeThumb2Branches()
1833             DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI);  in optimizeThumb2Branches()
1835               BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))  in optimizeThumb2Branches()
1836               .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());  in optimizeThumb2Branches()
1838             Br.MI->eraseFromParent();  in optimizeThumb2Branches()
1839             Br.MI = NewBR;  in optimizeThumb2Branches()