89   bool isThumb2;  member in __anoncf4d9d320111::ARMFastISel
102       isThumb2 = AFI->isThumbFunction();  in ARMFastISel()
520     unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;  in ARMMaterializeInt()
521     const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :  in ARMMaterializeInt()
533     bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :  in ARMMaterializeInt()
536       unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;  in ARMMaterializeInt()
537       const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :  in ARMMaterializeInt()
566   if (isThumb2)  in ARMMaterializeInt()
587   const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass  in ARMMaterializeGV()
607       Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;  in ARMMaterializeGV()
610       Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;  in ARMMaterializeGV()
637     if (isThumb2) {  in ARMMaterializeGV()
670     if (isThumb2)  in ARMMaterializeGV()
719     unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;  in fastMaterializeAlloca()
874         if (needsLowering && isThumb2)  in ARMSimplifyAddress()
893     const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass  in ARMSimplifyAddress()
896     unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;  in ARMSimplifyAddress()
973       if (isThumb2) {  in ARMEmitLoad()
986       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;  in ARMEmitLoad()
992       if (isThumb2) {  in ARMEmitLoad()
1001       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;  in ARMEmitLoad()
1007       if (isThumb2) {  in ARMEmitLoad()
1015       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;  in ARMEmitLoad()
1023         Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;  in ARMEmitLoad()
1024         RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;  in ARMEmitLoad()
1093       unsigned Res = createResultReg(isThumb2 ? &ARM::tGPRRegClass  in ARMEmitStore()
1095       unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;  in ARMEmitStore()
1103       if (isThumb2) {  in ARMEmitStore()
1116       if (isThumb2) {  in ARMEmitStore()
1130       if (isThumb2) {  in ARMEmitStore()
1149         StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;  in ARMEmitStore()
1279       unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;  in SelectBranch()
1290       unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;  in SelectBranch()
1303       unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;  in SelectBranch()
1329   unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;  in SelectBranch()
1342   unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;  in SelectBranch()
1354   unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;  in SelectIndirectBr()
1395       UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :  in ARMEmitCmp()
1424       if (isThumb2) {  in ARMEmitCmp()
1497   unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;  in SelectCmp()
1498   const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass  in SelectCmp()
1650     UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :  in SelectSelect()
1660   unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;  in SelectSelect()
1670     RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;  in SelectSelect()
1671     MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;  in SelectSelect()
1673     RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;  in SelectSelect()
1675       MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;  in SelectSelect()
1677       MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;  in SelectSelect()
1764       Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;  in SelectBinaryIntOp()
1767       Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;  in SelectBinaryIntOp()
1770       Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;  in SelectBinaryIntOp()
2153   unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;  in SelectRet()
2164     return isThumb2 ? ARM::tBLXr : ARM::BLX;  in ARMSelectCallOp()
2166     return isThumb2 ? ARM::tBL : ARM::BL;  in ARMSelectCallOp()
2255   if (isThumb2)  in ARMEmitLibcall()
2404   if(isThumb2)  in SelectCall()
2487     unsigned LdrOpc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;  in SelectIntrinsicCall()
2488     const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass  in SelectIntrinsicCall()
2678   bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];  in ARMEmitIntExt()
2679   const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];  in ARMEmitIntExt()
2680   const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];  in ARMEmitIntExt()
2691   unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;  in ARMEmitIntExt()
2758   if (isThumb2)  in SelectShift()
2922     if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&  in tryToFoldLoadIntoMI()
2952   if (isThumb2) {  in ARMLowerPICELF()