Lines Matching refs:is64BitVector
275 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1652 bool is64BitVector) { in GetVLDSTAlign() argument
1654 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1786 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
1787 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); in SelectVLD()
1814 if (!is64BitVector) in SelectVLD()
1830 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
1831 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
1895 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
1923 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
1924 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector); in SelectVST()
1956 if (is64BitVector || NumVecs <= 2) { in SelectVST()
1960 } else if (is64BitVector) { in SelectVST()
1982 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVST()
2072 bool is64BitVector = VT.is64BitVector(); in SelectVLDSTLane() local
2106 if (!is64BitVector) in SelectVLDSTLane()
2130 if (is64BitVector) in SelectVLDSTLane()
2139 if (is64BitVector) in SelectVLDSTLane()
2150 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLDSTLane()
2161 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0; in SelectVLDSTLane()