Lines Matching refs:lane
267 // Register list of one D register, with byte lane subscripting.
277 // ...with half-word lane subscripting.
287 // ...with word lane subscripting.
298 // Register list of two D registers with byte lane subscripting.
308 // ...with half-word lane subscripting.
318 // ...with word lane subscripting.
328 // Register list of two Q registers with half-word lane subscripting.
338 // ...with word lane subscripting.
350 // Register list of three D registers with byte lane subscripting.
360 // ...with half-word lane subscripting.
370 // ...with word lane subscripting.
380 // Register list of three Q registers with half-word lane subscripting.
390 // ...with word lane subscripting.
401 // Register list of four D registers with byte lane subscripting.
411 // ...with half-word lane subscripting.
421 // ...with word lane subscripting.
431 // Register list of four Q registers with half-word lane subscripting.
441 // ...with word lane subscripting.
1032 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1037 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1040 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1045 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1048 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1053 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1055 // VLD1LN : Vector Load (single element to one lane)
1059 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1060 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1064 imm:$lane))]> {
1071 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1072 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1076 imm:$lane))]> {
1083 imm:$lane))];
1087 let Inst{7-5} = lane{2-0};
1090 let Inst{7-6} = lane{1-0};
1094 let Inst{7} = lane{0};
1103 (f32 (load addrmode6:$addr)), imm:$lane),
1104 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1106 (f32 (load addrmode6:$addr)), imm:$lane),
1107 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1115 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1116 "\\{$Vd[$lane]\\}, $Rn$Rm",
1122 let Inst{7-5} = lane{2-0};
1125 let Inst{7-6} = lane{1-0};
1129 let Inst{7} = lane{0};
1138 // VLD2LN : Vector Load (single 2-element structure to one lane)
1141 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1142 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1150 let Inst{7-5} = lane{2-0};
1153 let Inst{7-6} = lane{1-0};
1156 let Inst{7} = lane{0};
1165 let Inst{7-6} = lane{1-0};
1168 let Inst{7} = lane{0};
1178 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1179 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1186 let Inst{7-5} = lane{2-0};
1189 let Inst{7-6} = lane{1-0};
1192 let Inst{7} = lane{0};
1200 let Inst{7-6} = lane{1-0};
1203 let Inst{7} = lane{0};
1209 // VLD3LN : Vector Load (single 3-element structure to one lane)
1213 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1214 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1221 let Inst{7-5} = lane{2-0};
1224 let Inst{7-6} = lane{1-0};
1227 let Inst{7} = lane{0};
1236 let Inst{7-6} = lane{1-0};
1239 let Inst{7} = lane{0};
1250 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1252 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1259 let Inst{7-5} = lane{2-0};
1262 let Inst{7-6} = lane{1-0};
1265 let Inst{7} = lane{0};
1273 let Inst{7-6} = lane{1-0};
1276 let Inst{7} = lane{0};
1282 // VLD4LN : Vector Load (single 4-element structure to one lane)
1287 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1288 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1296 let Inst{7-5} = lane{2-0};
1299 let Inst{7-6} = lane{1-0};
1302 let Inst{7} = lane{0};
1312 let Inst{7-6} = lane{1-0};
1315 let Inst{7} = lane{0};
1327 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1329 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1337 let Inst{7-5} = lane{2-0};
1340 let Inst{7-6} = lane{1-0};
1343 let Inst{7} = lane{0};
1352 let Inst{7-6} = lane{1-0};
1355 let Inst{7} = lane{0};
2033 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
2038 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2040 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
2045 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2047 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
2052 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2054 // VST1LN : Vector Store (single element from one lane)
2058 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2059 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2060 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
2066 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2072 let Inst{7-5} = lane{2-0};
2076 let Inst{7-6} = lane{1-0};
2082 let Inst{7} = lane{0};
2090 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
2091 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
2092 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2093 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2100 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2101 "\\{$Vd[$lane]\\}, $Rn$Rm",
2103 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2109 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2115 let Inst{7-5} = lane{2-0};
2119 let Inst{7-6} = lane{1-0};
2124 let Inst{7} = lane{0};
2134 // VST2LN : Vector Store (single 2-element structure from one lane)
2137 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2138 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2146 let Inst{7-5} = lane{2-0};
2149 let Inst{7-6} = lane{1-0};
2152 let Inst{7} = lane{0};
2161 let Inst{7-6} = lane{1-0};
2165 let Inst{7} = lane{0};
2176 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2177 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2184 let Inst{7-5} = lane{2-0};
2187 let Inst{7-6} = lane{1-0};
2190 let Inst{7} = lane{0};
2198 let Inst{7-6} = lane{1-0};
2201 let Inst{7} = lane{0};
2207 // VST3LN : Vector Store (single 3-element structure from one lane)
2211 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2212 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2218 let Inst{7-5} = lane{2-0};
2221 let Inst{7-6} = lane{1-0};
2224 let Inst{7} = lane{0};
2233 let Inst{7-6} = lane{1-0};
2236 let Inst{7} = lane{0};
2246 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2248 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2254 let Inst{7-5} = lane{2-0};
2257 let Inst{7-6} = lane{1-0};
2260 let Inst{7} = lane{0};
2268 let Inst{7-6} = lane{1-0};
2271 let Inst{7} = lane{0};
2277 // VST4LN : Vector Store (single 4-element structure from one lane)
2281 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2282 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2290 let Inst{7-5} = lane{2-0};
2293 let Inst{7-6} = lane{1-0};
2296 let Inst{7} = lane{0};
2306 let Inst{7-6} = lane{1-0};
2309 let Inst{7} = lane{0};
2320 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2322 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2329 let Inst{7-5} = lane{2-0};
2332 let Inst{7-6} = lane{1-0};
2335 let Inst{7} = lane{0};
2344 let Inst{7-6} = lane{1-0};
2347 let Inst{7} = lane{0};
2417 // Translate lane numbers from Q registers to D subregs.
2574 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2575 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2578 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2586 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2587 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2590 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2622 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2623 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2627 imm:$lane)))))]> {
2635 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2636 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2640 imm:$lane)))))]> {
2670 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2671 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2675 imm:$lane)))))]> {
2682 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2683 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2686 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2737 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2738 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2742 imm:$lane)))))]> {
2749 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2750 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2754 imm:$lane)))))]> {
2783 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2785 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2790 imm:$lane)))))))]>;
2796 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2798 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2803 imm:$lane)))))))]>;
2818 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2820 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2825 imm:$lane)))))))]>;
2832 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2834 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2839 imm:$lane)))))))]>;
2892 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2894 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2899 imm:$lane))))))]>;
2904 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2906 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2911 imm:$lane))))))]>;
2940 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2942 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2947 imm:$lane)))))]>;
2953 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2955 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2960 imm:$lane)))))]>;
2988 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2989 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2992 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2997 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2998 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3001 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
3053 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3054 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3058 imm:$lane)))))]>;
3063 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3064 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3068 imm:$lane)))))]>;
4169 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4172 (DSubReg_i16_reg imm:$lane))),
4173 (SubReg_i16_lane imm:$lane)))>;
4175 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4178 (DSubReg_i32_reg imm:$lane))),
4179 (SubReg_i32_lane imm:$lane)))>;
4181 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4184 (DSubReg_i32_reg imm:$lane))),
4185 (SubReg_i32_lane imm:$lane)))>;
4207 imm:$lane)))),
4210 (DSubReg_i16_reg imm:$lane))),
4211 (SubReg_i16_lane imm:$lane)))>;
4214 imm:$lane)))),
4217 (DSubReg_i32_reg imm:$lane))),
4218 (SubReg_i32_lane imm:$lane)))>;
4229 imm:$lane)))),
4232 (DSubReg_i16_reg imm:$lane))),
4233 (SubReg_i16_lane imm:$lane)))>;
4236 imm:$lane)))),
4239 (DSubReg_i32_reg imm:$lane))),
4240 (SubReg_i32_lane imm:$lane)))>;
4286 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4289 (DSubReg_i16_reg imm:$lane))),
4290 (SubReg_i16_lane imm:$lane)))>;
4294 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4297 (DSubReg_i32_reg imm:$lane))),
4298 (SubReg_i32_lane imm:$lane)))>;
4302 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4306 (DSubReg_i32_reg imm:$lane))),
4307 (SubReg_i32_lane imm:$lane)))>,
4355 imm:$lane)))))),
4357 imm:$lane))>;
4363 imm:$lane)))))),
4365 imm:$lane))>;
4371 imm:$lane)))))),
4376 (DSubReg_i16_reg imm:$lane))),
4377 (SubReg_i16_lane imm:$lane)))>;
4383 imm:$lane)))))),
4388 (DSubReg_i32_reg imm:$lane))),
4389 (SubReg_i32_lane imm:$lane)))>;
4425 imm:$lane)))))),
4426 (v4i16 (VQRDMLSHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))>;
4432 imm:$lane)))))),
4434 imm:$lane))>;
4440 imm:$lane)))))),
4445 (DSubReg_i16_reg imm:$lane))),
4446 (SubReg_i16_lane imm:$lane)))>;
4452 imm:$lane)))))),
4457 (DSubReg_i32_reg imm:$lane))),
4458 (SubReg_i32_lane imm:$lane)))>;
4476 imm:$lane)))))),
4477 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4481 imm:$lane)))))),
4482 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4504 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4507 (DSubReg_i16_reg imm:$lane))),
4508 (SubReg_i16_lane imm:$lane)))>;
4512 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4515 (DSubReg_i32_reg imm:$lane))),
4516 (SubReg_i32_lane imm:$lane)))>;
4520 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4523 (DSubReg_i32_reg imm:$lane))),
4524 (SubReg_i32_lane imm:$lane)))>,
4552 imm:$lane)))))),
4553 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4557 imm:$lane)))))),
4558 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
5556 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5557 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
5559 imm:$lane))]> {
5560 let Inst{21} = lane{2};
5561 let Inst{6-5} = lane{1-0};
5564 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5565 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
5567 imm:$lane))]> {
5568 let Inst{21} = lane{1};
5569 let Inst{6} = lane{0};
5572 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5573 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5575 imm:$lane))]> {
5576 let Inst{21} = lane{2};
5577 let Inst{6-5} = lane{1-0};
5580 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5581 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5583 imm:$lane))]> {
5584 let Inst{21} = lane{1};
5585 let Inst{6} = lane{0};
5588 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5589 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5591 imm:$lane))]>,
5593 let Inst{21} = lane{0};
5596 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5598 (DSubReg_i8_reg imm:$lane))),
5599 (SubReg_i8_lane imm:$lane))>;
5600 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5602 (DSubReg_i16_reg imm:$lane))),
5603 (SubReg_i16_lane imm:$lane))>;
5604 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5606 (DSubReg_i8_reg imm:$lane))),
5607 (SubReg_i8_lane imm:$lane))>;
5608 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5610 (DSubReg_i16_reg imm:$lane))),
5611 (SubReg_i16_lane imm:$lane))>;
5612 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5614 (DSubReg_i32_reg imm:$lane))),
5615 (SubReg_i32_lane imm:$lane))>,
5617 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5619 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5621 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5623 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5641 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5642 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5644 GPR:$R, imm:$lane))]> {
5645 let Inst{21} = lane{2};
5646 let Inst{6-5} = lane{1-0};
5649 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5650 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5652 GPR:$R, imm:$lane))]> {
5653 let Inst{21} = lane{1};
5654 let Inst{6} = lane{0};
5657 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5658 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5660 GPR:$R, imm:$lane))]>,
5662 let Inst{21} = lane{0};
5668 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5671 (DSubReg_i8_reg imm:$lane))),
5672 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5673 (DSubReg_i8_reg imm:$lane)))>;
5674 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5677 (DSubReg_i16_reg imm:$lane))),
5678 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5679 (DSubReg_i16_reg imm:$lane)))>;
5680 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5683 (DSubReg_i32_reg imm:$lane))),
5684 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5685 (DSubReg_i32_reg imm:$lane)))>;
5760 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5761 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5762 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5766 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5767 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5769 VectorIndex32:$lane)))]>;
5774 bits<3> lane;
5775 let Inst{19-17} = lane{2-0};
5778 bits<2> lane;
5779 let Inst{19-18} = lane{1-0};
5782 bits<1> lane;
5783 let Inst{19} = lane{0};
5786 bits<3> lane;
5787 let Inst{19-17} = lane{2-0};
5790 bits<2> lane;
5791 let Inst{19-18} = lane{1-0};
5794 bits<1> lane;
5795 let Inst{19} = lane{0};
5798 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5799 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5801 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5802 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5804 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5806 (DSubReg_i8_reg imm:$lane))),
5807 (SubReg_i8_lane imm:$lane)))>;
5808 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5810 (DSubReg_i16_reg imm:$lane))),
5811 (SubReg_i16_lane imm:$lane)))>;
5812 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5814 (DSubReg_i32_reg imm:$lane))),
5815 (SubReg_i32_lane imm:$lane)))>;
5816 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5818 (DSubReg_i32_reg imm:$lane))),
5819 (SubReg_i32_lane imm:$lane)))>;
6350 def : VFPPat<(f64 (sint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
6351 (VSITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6352 def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6353 (VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6354 def : VFPPat<(f64 (uint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
6355 (VUITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6356 def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6357 (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6511 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6512 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6840 // VLD1 single-lane pseudo-instructions. These need special handling for
6841 // the lane index that an InstAlias can't handle, so we use these instead.
6878 // VST1 single-lane pseudo-instructions. These need special handling for
6879 // the lane index that an InstAlias can't handle, so we use these instead.
6915 // VLD2 single-lane pseudo-instructions. These need special handling for
6916 // the lane index that an InstAlias can't handle, so we use these instead.
6974 // VST2 single-lane pseudo-instructions. These need special handling for
6975 // the lane index that an InstAlias can't handle, so we use these instead.
7034 // the lane index that an InstAlias can't handle, so we use these instead.
7104 // VLD3 single-lane pseudo-instructions. These need special handling for
7105 // the lane index that an InstAlias can't handle, so we use these instead.
7222 // VST3 single-lane pseudo-instructions. These need special handling for
7223 // the lane index that an InstAlias can't handle, so we use these instead.
7342 // the lane index that an InstAlias can't handle, so we use these instead.
7412 // VLD4 single-lane pseudo-instructions. These need special handling for
7413 // the lane index that an InstAlias can't handle, so we use these instead.
7544 // VST4 single-lane pseudo-instructions. These need special handling for
7545 // the lane index that an InstAlias can't handle, so we use these instead.