Lines Matching refs:lanes

197 // Register list of one D register, with "all lanes" subscripting.
206 // Register list of two D registers, with "all lanes" subscripting.
226 // Register list of three D registers, with "all lanes" subscripting.
246 // Register list of four D registers, with "all lanes" subscripting.
1364 //   VLD1DUP  : Vector Load (single element to all lanes)
1457 //   VLD2DUP  : Vector Load (single 2-element structure to all lanes)
1520 //   VLD3DUP  : Vector Load (single 3-element structure to all lanes)
1565 //   VLD4DUP  : Vector Load (single 4-element structure to all lanes)
6541 // half the lanes available. Example:
6658 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
7033 // VLD3 all-lanes pseudo-instructions. These need special handling for
7341 // VLD4 all-lanes pseudo-instructions. These need special handling for