210   for (auto &VA : ArgLocs) {  in LowerFormalArguments()  local
211     if (VA.isRegLoc()) {  in LowerFormalArguments()
213       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()
222         RegInfo.addLiveIn(VA.getLocReg(), VReg);  in LowerFormalArguments()
228         if (VA.getLocInfo() == CCValAssign::SExt)  in LowerFormalArguments()
230                                  DAG.getValueType(VA.getValVT()));  in LowerFormalArguments()
231         else if (VA.getLocInfo() == CCValAssign::ZExt)  in LowerFormalArguments()
233                                  DAG.getValueType(VA.getValVT()));  in LowerFormalArguments()
235         if (VA.getLocInfo() != CCValAssign::Full)  in LowerFormalArguments()
236           ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);  in LowerFormalArguments()
312     CCValAssign &VA = ArgLocs[i];  in LowerCall()  local
316     switch (VA.getLocInfo()) {  in LowerCall()
322       Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);  in LowerCall()
325       Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);  in LowerCall()
328       Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);  in LowerCall()
333     if (VA.isRegLoc())  in LowerCall()
334       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));  in LowerCall()
415     CCValAssign &VA = RVLocs[i];  in LowerReturn()  local
416     assert(VA.isRegLoc() && "Can only return in registers!");  in LowerReturn()
418     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);  in LowerReturn()
423     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));  in LowerReturn()