73                                   SmallVectorImpl<MachineOperand> &Cond) const {  in AnalyzeCondBr()
80   Cond.push_back(MachineOperand::CreateImm(Opc));  in AnalyzeCondBr()
83     Cond.push_back(Inst->getOperand(i));  in AnalyzeCondBr()
89                                   SmallVectorImpl<MachineOperand> &Cond,  in AnalyzeBranch()  argument
92   BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);  in AnalyzeBranch()
100                            const SmallVectorImpl<MachineOperand> &Cond) const {  in BuildCondBr()
101   unsigned Opc = Cond[0].getImm();  in BuildCondBr()
105   for (unsigned i = 1; i < Cond.size(); ++i) {  in BuildCondBr()
106     if (Cond[i].isReg())  in BuildCondBr()
107       MIB.addReg(Cond[i].getReg());  in BuildCondBr()
108     else if (Cond[i].isImm())  in BuildCondBr()
109       MIB.addImm(Cond[i].getImm());  in BuildCondBr()
118     const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {  in InsertBranch()  argument
127   assert((Cond.size() <= 3) &&  in InsertBranch()
132     BuildCondBr(MBB, TBB, DL, Cond);  in InsertBranch()
139   if (Cond.empty())  in InsertBranch()
142     BuildCondBr(MBB, TBB, DL, Cond);  in InsertBranch()
171     SmallVectorImpl<MachineOperand> &Cond) const {  in ReverseBranchCondition()
172   assert( (Cond.size() && Cond.size() <= 3) &&  in ReverseBranchCondition()
174   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));  in ReverseBranchCondition()
180     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,  in AnalyzeBranch()  argument
226     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);  in AnalyzeBranch()
255   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);  in AnalyzeBranch()