Lines Matching refs:STI
51 const MCSubtargetInfo &STI) const;
54 const MCSubtargetInfo &STI) const;
57 const MCSubtargetInfo &STI) const;
60 const MCSubtargetInfo &STI) const;
63 const MCSubtargetInfo &STI) const;
66 const MCSubtargetInfo &STI) const;
69 const MCSubtargetInfo &STI) const;
72 const MCSubtargetInfo &STI) const;
75 const MCSubtargetInfo &STI) const;
78 const MCSubtargetInfo &STI) const;
81 const MCSubtargetInfo &STI) const;
84 const MCSubtargetInfo &STI) const;
87 const MCSubtargetInfo &STI) const;
93 const MCSubtargetInfo &STI) const;
99 const MCSubtargetInfo &STI) const;
102 const MCSubtargetInfo &STI) const override { in EncodeInstruction()
111 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); in EncodeInstruction()
172 const MCSubtargetInfo &STI) const { in getDirectBrEncoding()
174 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
184 const MCSubtargetInfo &STI) const { in getCondBrEncoding()
186 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
197 const MCSubtargetInfo &STI) const { in getAbsDirectBrEncoding()
199 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
210 const MCSubtargetInfo &STI) const { in getAbsCondBrEncoding()
212 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
222 const MCSubtargetInfo &STI) const { in getImm16Encoding()
224 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
234 const MCSubtargetInfo &STI) const { in getMemRIEncoding()
238 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; in getMemRIEncoding()
242 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; in getMemRIEncoding()
253 const MCSubtargetInfo &STI) const { in getMemRIXEncoding()
257 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; in getMemRIXEncoding()
261 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; in getMemRIXEncoding()
272 const MCSubtargetInfo &STI) in getSPE8DisEncoding()
277 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE8DisEncoding()
281 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3; in getSPE8DisEncoding()
288 const MCSubtargetInfo &STI) in getSPE4DisEncoding()
293 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE4DisEncoding()
297 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2; in getSPE4DisEncoding()
304 const MCSubtargetInfo &STI) in getSPE2DisEncoding()
309 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 5; in getSPE2DisEncoding()
313 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 1; in getSPE2DisEncoding()
320 const MCSubtargetInfo &STI) const { in getTLSRegEncoding()
322 if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); in getTLSRegEncoding()
329 Triple TT(STI.getTargetTriple()); in getTLSRegEncoding()
336 const MCSubtargetInfo &STI) const { in getTLSCallEncoding()
343 return getDirectBrEncoding(MI, OpNo, Fixups, STI); in getTLSCallEncoding()
349 const MCSubtargetInfo &STI) const { in get_crbitm_encoding()
361 const MCSubtargetInfo &STI) const { in getMachineOpValue()