Lines Matching refs:Enable
52 "Enable 64-bit instructions">;
54 "Enable 64-bit registers usage for ppc32 [beta]">;
58 "Enable Altivec instructions">;
60 "Enable SPE instructions">;
62 "Enable the MFOCRF instruction">;
64 "Enable the fsqrt instruction">;
66 "Enable the fcpsgn instruction">;
68 "Enable the fre instruction">;
70 "Enable the fres instruction">;
72 "Enable the frsqrte instruction">;
74 "Enable the frsqrtes instruction">;
78 "Enable the stfiwx instruction">;
80 "Enable the lfiwax instruction">;
82 "Enable the fri[mnpz] instructions">;
84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
86 "Enable the isel instruction">;
88 "Enable the popcnt[dw] instructions">;
90 "Enable the bpermd instruction">;
92 "Enable extended divide instructions">;
94 "Enable the ldbrx instruction">;
96 "Enable the cmpb instruction">;
98 "Enable icbt instruction">;
100 "Enable Book E instructions",
106 "Enable E500/E500mc instructions">;
108 "Enable PPC 4xx instructions">;
110 "Enable PPC 6xx instructions">;
112 "Enable QPX instructions">;
114 "Enable VSX instructions",
117 "Enable POWER8 Altivec instructions",
120 "Enable POWER8 Crypto instructions",
123 "Enable POWER8 vector instructions",
127 "Enable Power8 direct move instructions",
131 "Enable l[bh]arx and st[bh]cx.">;
137 "Enable Hardware Transactional Memory instructions">;