Lines Matching refs:MVT
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
78 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in PPCTargetLowering()
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
91 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
98 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
106 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
107 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
108 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
109 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
110 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
112 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
113 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
117 setOperationAction(ISD::LOAD, MVT::i1, Custom); in PPCTargetLowering()
118 setOperationAction(ISD::STORE, MVT::i1, Custom); in PPCTargetLowering()
122 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); in PPCTargetLowering()
124 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
127 setTruncStoreAction(VT, MVT::i1, Expand); in PPCTargetLowering()
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); in PPCTargetLowering()
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); in PPCTargetLowering()
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); in PPCTargetLowering()
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); in PPCTargetLowering()
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand); in PPCTargetLowering()
146 setOperationAction(ISD::SREM, MVT::i32, Expand); in PPCTargetLowering()
147 setOperationAction(ISD::UREM, MVT::i32, Expand); in PPCTargetLowering()
148 setOperationAction(ISD::SREM, MVT::i64, Expand); in PPCTargetLowering()
149 setOperationAction(ISD::UREM, MVT::i64, Expand); in PPCTargetLowering()
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in PPCTargetLowering()
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in PPCTargetLowering()
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in PPCTargetLowering()
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in PPCTargetLowering()
162 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
163 setOperationAction(ISD::FCOS , MVT::f64, Expand); in PPCTargetLowering()
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in PPCTargetLowering()
165 setOperationAction(ISD::FREM , MVT::f64, Expand); in PPCTargetLowering()
166 setOperationAction(ISD::FPOW , MVT::f64, Expand); in PPCTargetLowering()
167 setOperationAction(ISD::FMA , MVT::f64, Legal); in PPCTargetLowering()
168 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
169 setOperationAction(ISD::FCOS , MVT::f32, Expand); in PPCTargetLowering()
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in PPCTargetLowering()
171 setOperationAction(ISD::FREM , MVT::f32, Expand); in PPCTargetLowering()
172 setOperationAction(ISD::FPOW , MVT::f32, Expand); in PPCTargetLowering()
173 setOperationAction(ISD::FMA , MVT::f32, Legal); in PPCTargetLowering()
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); in PPCTargetLowering()
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal); in PPCTargetLowering()
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal); in PPCTargetLowering()
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in PPCTargetLowering()
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in PPCTargetLowering()
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in PPCTargetLowering()
200 setOperationAction(ISD::FROUND, MVT::f64, Legal); in PPCTargetLowering()
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in PPCTargetLowering()
205 setOperationAction(ISD::FROUND, MVT::f32, Legal); in PPCTargetLowering()
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand); in PPCTargetLowering()
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); in PPCTargetLowering()
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); in PPCTargetLowering()
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); in PPCTargetLowering()
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); in PPCTargetLowering()
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); in PPCTargetLowering()
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); in PPCTargetLowering()
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); in PPCTargetLowering()
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal); in PPCTargetLowering()
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal); in PPCTargetLowering()
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); in PPCTargetLowering()
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); in PPCTargetLowering()
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand); in PPCTargetLowering()
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand); in PPCTargetLowering()
232 setOperationAction(ISD::SELECT, MVT::i32, Expand); in PPCTargetLowering()
233 setOperationAction(ISD::SELECT, MVT::i64, Expand); in PPCTargetLowering()
234 setOperationAction(ISD::SELECT, MVT::f32, Expand); in PPCTargetLowering()
235 setOperationAction(ISD::SELECT, MVT::f64, Expand); in PPCTargetLowering()
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
244 setOperationAction(ISD::SETCC, MVT::i32, Custom); in PPCTargetLowering()
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in PPCTargetLowering()
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in PPCTargetLowering()
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in PPCTargetLowering()
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in PPCTargetLowering()
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in PPCTargetLowering()
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in PPCTargetLowering()
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); in PPCTargetLowering()
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); in PPCTargetLowering()
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in PPCTargetLowering()
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in PPCTargetLowering()
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in PPCTargetLowering()
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in PPCTargetLowering()
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in PPCTargetLowering()
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in PPCTargetLowering()
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in PPCTargetLowering()
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); in PPCTargetLowering()
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); in PPCTargetLowering()
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom); in PPCTargetLowering()
290 setOperationAction(ISD::TRAP, MVT::Other, Legal); in PPCTargetLowering()
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
297 setOperationAction(ISD::VASTART , MVT::Other, Custom); in PPCTargetLowering()
302 setOperationAction(ISD::VAARG, MVT::i1, Promote); in PPCTargetLowering()
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64); in PPCTargetLowering()
304 setOperationAction(ISD::VAARG, MVT::i8, Promote); in PPCTargetLowering()
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64); in PPCTargetLowering()
306 setOperationAction(ISD::VAARG, MVT::i16, Promote); in PPCTargetLowering()
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64); in PPCTargetLowering()
308 setOperationAction(ISD::VAARG, MVT::i32, Promote); in PPCTargetLowering()
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64); in PPCTargetLowering()
310 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
313 setOperationAction(ISD::VAARG, MVT::Other, Custom); in PPCTargetLowering()
314 setOperationAction(ISD::VAARG, MVT::i64, Custom); in PPCTargetLowering()
317 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom); in PPCTargetLowering()
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in PPCTargetLowering()
326 setOperationAction(ISD::VAEND , MVT::Other, Expand); in PPCTargetLowering()
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in PPCTargetLowering()
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); in PPCTargetLowering()
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in PPCTargetLowering()
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); in PPCTargetLowering()
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in PPCTargetLowering()
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); in PPCTargetLowering()
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in PPCTargetLowering()
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); in PPCTargetLowering()
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in PPCTargetLowering()
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in PPCTargetLowering()
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in PPCTargetLowering()
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); in PPCTargetLowering()
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering()
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering()
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in PPCTargetLowering()
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in PPCTargetLowering()
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in PPCTargetLowering()
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); in PPCTargetLowering()
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); in PPCTargetLowering()
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in PPCTargetLowering()
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); in PPCTargetLowering()
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in PPCTargetLowering()
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); in PPCTargetLowering()
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in PPCTargetLowering()
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
403 for (MVT VT : MVT::vector_valuetypes()) { in PPCTargetLowering()
420 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
424 AddPromotedToType (ISD::AND , VT, MVT::v4i32); in PPCTargetLowering()
426 AddPromotedToType (ISD::OR , VT, MVT::v4i32); in PPCTargetLowering()
428 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); in PPCTargetLowering()
430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); in PPCTargetLowering()
432 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); in PPCTargetLowering()
434 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); in PPCTargetLowering()
478 for (MVT InnerVT : MVT::vector_valuetypes()) { in PPCTargetLowering()
488 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
490 setOperationAction(ISD::AND , MVT::v4i32, Legal); in PPCTargetLowering()
491 setOperationAction(ISD::OR , MVT::v4i32, Legal); in PPCTargetLowering()
492 setOperationAction(ISD::XOR , MVT::v4i32, Legal); in PPCTargetLowering()
493 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); in PPCTargetLowering()
494 setOperationAction(ISD::SELECT, MVT::v4i32, in PPCTargetLowering()
496 setOperationAction(ISD::STORE , MVT::v4i32, Legal); in PPCTargetLowering()
497 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
498 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); in PPCTargetLowering()
499 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
500 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
501 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
502 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
503 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
504 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
506 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
507 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
508 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
509 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
511 setOperationAction(ISD::MUL, MVT::v4f32, Legal); in PPCTargetLowering()
512 setOperationAction(ISD::FMA, MVT::v4f32, Legal); in PPCTargetLowering()
515 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
516 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
521 setOperationAction(ISD::MUL, MVT::v4i32, Legal); in PPCTargetLowering()
523 setOperationAction(ISD::MUL, MVT::v4i32, Custom); in PPCTargetLowering()
525 setOperationAction(ISD::MUL, MVT::v8i16, Custom); in PPCTargetLowering()
526 setOperationAction(ISD::MUL, MVT::v16i8, Custom); in PPCTargetLowering()
528 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
529 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
531 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); in PPCTargetLowering()
532 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); in PPCTargetLowering()
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
537 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); in PPCTargetLowering()
538 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); in PPCTargetLowering()
539 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); in PPCTargetLowering()
540 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand); in PPCTargetLowering()
543 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
544 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
546 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
547 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
548 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
549 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
550 setOperationAction(ISD::FROUND, MVT::v2f64, Legal); in PPCTargetLowering()
552 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
554 setOperationAction(ISD::MUL, MVT::v2f64, Legal); in PPCTargetLowering()
555 setOperationAction(ISD::FMA, MVT::v2f64, Legal); in PPCTargetLowering()
557 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
558 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
560 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); in PPCTargetLowering()
561 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal); in PPCTargetLowering()
562 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); in PPCTargetLowering()
563 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
564 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); in PPCTargetLowering()
567 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand); in PPCTargetLowering()
568 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); in PPCTargetLowering()
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand); in PPCTargetLowering()
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand); in PPCTargetLowering()
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); in PPCTargetLowering()
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal); in PPCTargetLowering()
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal); in PPCTargetLowering()
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass); in PPCTargetLowering()
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass); in PPCTargetLowering()
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass); in PPCTargetLowering()
583 setOperationAction(ISD::SHL, MVT::v2i64, Legal); in PPCTargetLowering()
584 setOperationAction(ISD::SRA, MVT::v2i64, Legal); in PPCTargetLowering()
585 setOperationAction(ISD::SRL, MVT::v2i64, Legal); in PPCTargetLowering()
587 setOperationAction(ISD::SETCC, MVT::v2i64, Legal); in PPCTargetLowering()
590 setOperationAction(ISD::SHL, MVT::v2i64, Expand); in PPCTargetLowering()
591 setOperationAction(ISD::SRA, MVT::v2i64, Expand); in PPCTargetLowering()
592 setOperationAction(ISD::SRL, MVT::v2i64, Expand); in PPCTargetLowering()
594 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in PPCTargetLowering()
597 setOperationAction(ISD::ADD, MVT::v2i64, Expand); in PPCTargetLowering()
598 setOperationAction(ISD::SUB, MVT::v2i64, Expand); in PPCTargetLowering()
601 setOperationAction(ISD::LOAD, MVT::v2i64, Promote); in PPCTargetLowering()
602 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
603 setOperationAction(ISD::STORE, MVT::v2i64, Promote); in PPCTargetLowering()
604 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
606 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal); in PPCTargetLowering()
608 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
609 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
610 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
611 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal); in PPCTargetLowering()
615 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal); in PPCTargetLowering()
616 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in PPCTargetLowering()
617 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); in PPCTargetLowering()
618 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); in PPCTargetLowering()
620 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); in PPCTargetLowering()
624 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass); in PPCTargetLowering()
628 setOperationAction(ISD::FADD, MVT::v4f64, Legal); in PPCTargetLowering()
629 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); in PPCTargetLowering()
630 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); in PPCTargetLowering()
631 setOperationAction(ISD::FREM, MVT::v4f64, Expand); in PPCTargetLowering()
633 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal); in PPCTargetLowering()
634 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand); in PPCTargetLowering()
636 setOperationAction(ISD::LOAD , MVT::v4f64, Custom); in PPCTargetLowering()
637 setOperationAction(ISD::STORE , MVT::v4f64, Custom); in PPCTargetLowering()
639 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
640 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom); in PPCTargetLowering()
643 setOperationAction(ISD::SELECT, MVT::v4f64, Expand); in PPCTargetLowering()
644 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); in PPCTargetLowering()
646 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal); in PPCTargetLowering()
647 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand); in PPCTargetLowering()
648 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand); in PPCTargetLowering()
649 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand); in PPCTargetLowering()
650 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom); in PPCTargetLowering()
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal); in PPCTargetLowering()
652 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); in PPCTargetLowering()
654 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal); in PPCTargetLowering()
655 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand); in PPCTargetLowering()
657 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); in PPCTargetLowering()
658 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand); in PPCTargetLowering()
659 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal); in PPCTargetLowering()
661 setOperationAction(ISD::FNEG , MVT::v4f64, Legal); in PPCTargetLowering()
662 setOperationAction(ISD::FABS , MVT::v4f64, Legal); in PPCTargetLowering()
663 setOperationAction(ISD::FSIN , MVT::v4f64, Expand); in PPCTargetLowering()
664 setOperationAction(ISD::FCOS , MVT::v4f64, Expand); in PPCTargetLowering()
665 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand); in PPCTargetLowering()
666 setOperationAction(ISD::FPOW , MVT::v4f64, Expand); in PPCTargetLowering()
667 setOperationAction(ISD::FLOG , MVT::v4f64, Expand); in PPCTargetLowering()
668 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand); in PPCTargetLowering()
669 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand); in PPCTargetLowering()
670 setOperationAction(ISD::FEXP , MVT::v4f64, Expand); in PPCTargetLowering()
671 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand); in PPCTargetLowering()
673 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal); in PPCTargetLowering()
674 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal); in PPCTargetLowering()
676 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal); in PPCTargetLowering()
677 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal); in PPCTargetLowering()
679 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass); in PPCTargetLowering()
681 setOperationAction(ISD::FADD, MVT::v4f32, Legal); in PPCTargetLowering()
682 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); in PPCTargetLowering()
683 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); in PPCTargetLowering()
684 setOperationAction(ISD::FREM, MVT::v4f32, Expand); in PPCTargetLowering()
686 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal); in PPCTargetLowering()
687 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand); in PPCTargetLowering()
689 setOperationAction(ISD::LOAD , MVT::v4f32, Custom); in PPCTargetLowering()
690 setOperationAction(ISD::STORE , MVT::v4f32, Custom); in PPCTargetLowering()
693 setOperationAction(ISD::SELECT, MVT::v4f32, Expand); in PPCTargetLowering()
694 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); in PPCTargetLowering()
696 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal); in PPCTargetLowering()
697 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand); in PPCTargetLowering()
698 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand); in PPCTargetLowering()
699 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand); in PPCTargetLowering()
700 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom); in PPCTargetLowering()
701 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
702 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
704 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal); in PPCTargetLowering()
705 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand); in PPCTargetLowering()
707 setOperationAction(ISD::FNEG , MVT::v4f32, Legal); in PPCTargetLowering()
708 setOperationAction(ISD::FABS , MVT::v4f32, Legal); in PPCTargetLowering()
709 setOperationAction(ISD::FSIN , MVT::v4f32, Expand); in PPCTargetLowering()
710 setOperationAction(ISD::FCOS , MVT::v4f32, Expand); in PPCTargetLowering()
711 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand); in PPCTargetLowering()
712 setOperationAction(ISD::FPOW , MVT::v4f32, Expand); in PPCTargetLowering()
713 setOperationAction(ISD::FLOG , MVT::v4f32, Expand); in PPCTargetLowering()
714 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand); in PPCTargetLowering()
715 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand); in PPCTargetLowering()
716 setOperationAction(ISD::FEXP , MVT::v4f32, Expand); in PPCTargetLowering()
717 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand); in PPCTargetLowering()
719 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in PPCTargetLowering()
720 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal); in PPCTargetLowering()
722 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal); in PPCTargetLowering()
723 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal); in PPCTargetLowering()
725 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass); in PPCTargetLowering()
727 setOperationAction(ISD::AND , MVT::v4i1, Legal); in PPCTargetLowering()
728 setOperationAction(ISD::OR , MVT::v4i1, Legal); in PPCTargetLowering()
729 setOperationAction(ISD::XOR , MVT::v4i1, Legal); in PPCTargetLowering()
732 setOperationAction(ISD::SELECT, MVT::v4i1, Expand); in PPCTargetLowering()
733 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal); in PPCTargetLowering()
735 setOperationAction(ISD::LOAD , MVT::v4i1, Custom); in PPCTargetLowering()
736 setOperationAction(ISD::STORE , MVT::v4i1, Custom); in PPCTargetLowering()
738 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom); in PPCTargetLowering()
739 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand); in PPCTargetLowering()
740 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand); in PPCTargetLowering()
741 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand); in PPCTargetLowering()
742 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom); in PPCTargetLowering()
743 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand); in PPCTargetLowering()
744 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom); in PPCTargetLowering()
746 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom); in PPCTargetLowering()
747 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom); in PPCTargetLowering()
749 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass); in PPCTargetLowering()
751 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal); in PPCTargetLowering()
752 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in PPCTargetLowering()
753 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal); in PPCTargetLowering()
754 setOperationAction(ISD::FROUND, MVT::v4f64, Legal); in PPCTargetLowering()
756 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
757 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
758 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
759 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
761 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand); in PPCTargetLowering()
762 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand); in PPCTargetLowering()
765 setOperationAction(ISD::FRINT, MVT::v4f64, Expand); in PPCTargetLowering()
766 setOperationAction(ISD::FRINT, MVT::v4f32, Expand); in PPCTargetLowering()
769 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); in PPCTargetLowering()
770 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); in PPCTargetLowering()
772 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
773 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
775 setOperationAction(ISD::FDIV, MVT::v4f64, Expand); in PPCTargetLowering()
776 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand); in PPCTargetLowering()
778 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in PPCTargetLowering()
779 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in PPCTargetLowering()
784 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); in PPCTargetLowering()
786 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
789 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); in PPCTargetLowering()
790 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); in PPCTargetLowering()
1043 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1046 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements()); in getSetCCResultType()
1149 if (N->getValueType(0) != MVT::v16i8) in isVMerge()
1224 if (N->getValueType(0) != MVT::v16i8) in isVSLDOIShuffleMask()
1267 assert(N->getValueType(0) == MVT::v16i8 && in isSplatShuffleMask()
1352 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef in get_VSPLTI_elt()
1355 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) in get_VSPLTI_elt()
1359 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef in get_VSPLTI_elt()
1362 return DAG.getTargetConstant(Val, MVT::i32); in get_VSPLTI_elt()
1384 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); in get_VSPLTI_elt()
1406 return DAG.getTargetConstant(MaskVal, MVT::i32); in get_VSPLTI_elt()
1414 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1) in isQVALIGNIShuffleMask()
1453 if (N->getValueType(0) == MVT::i32) in isIntS16Immediate()
1517 if (VT != MVT::i64) in fixupFuncForFI()
1623 if ((CN->getValueType(0) == MVT::i32 || in SelectAddressRegImm()
1629 Disp = DAG.getTargetConstant((short)Addr, MVT::i32); in SelectAddressRegImm()
1631 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); in SelectAddressRegImm()
1632 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; in SelectAddressRegImm()
1702 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) { in getPreIndexedAddressParts()
1734 if (VT != MVT::i64) { in getPreIndexedAddressParts()
1749 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && in getPreIndexedAddressParts()
1825 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; in getTOCEntry()
1831 DAG.getVTList(VT, MVT::Other), Ops, VT, in getTOCEntry()
1939 is64bit ? MVT::i64 : MVT::i32); in LowerGlobalTLSAddress()
1951 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddress()
1966 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddress()
1984 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddress()
2048 if (Op.getValueType() == MVT::v2i64) { in LowerSETCC()
2051 if (Op.getOperand(0).getValueType() == MVT::v2i64) { in LowerSETCC()
2055 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, in LowerSETCC()
2056 DAG.getSetCC(dl, MVT::v4i32, in LowerSETCC()
2057 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)), in LowerSETCC()
2058 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)), in LowerSETCC()
2076 if (VT.bitsLT(MVT::i32)) { in LowerSETCC()
2077 VT = MVT::i32; in LowerSETCC()
2083 DAG.getConstant(Log2b, MVT::i32)); in LowerSETCC()
2084 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); in LowerSETCC()
2121 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
2122 VAListPtr, MachinePointerInfo(SV), MVT::i8, in LowerVAARG()
2126 if (VT == MVT::i64) { in LowerVAARG()
2128 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, in LowerVAARG()
2129 DAG.getConstant(1, MVT::i32)); in LowerVAARG()
2130 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, in LowerVAARG()
2131 DAG.getConstant(0, MVT::i32), ISD::SETNE); in LowerVAARG()
2132 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, in LowerVAARG()
2133 DAG.getConstant(1, MVT::i32)); in LowerVAARG()
2135 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, in LowerVAARG()
2141 DAG.getConstant(1, MVT::i32)); in LowerVAARG()
2144 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
2145 FprPtr, MachinePointerInfo(SV), MVT::i8, in LowerVAARG()
2150 DAG.getConstant(8, MVT::i32)); in LowerVAARG()
2153 DAG.getConstant(4, MVT::i32)); in LowerVAARG()
2156 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, in LowerVAARG()
2161 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, in LowerVAARG()
2167 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, in LowerVAARG()
2168 DAG.getConstant(8, MVT::i32), ISD::SETLT); in LowerVAARG()
2171 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, in LowerVAARG()
2174 MVT::i32)); in LowerVAARG()
2183 DAG.getConstant(32, MVT::i32)); in LowerVAARG()
2186 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, in LowerVAARG()
2188 DAG.getConstant(VT == MVT::i64 ? 2 : 1, in LowerVAARG()
2189 MVT::i32)); in LowerVAARG()
2194 MVT::i8, false, false, 0); in LowerVAARG()
2202 MVT::i32)); in LowerVAARG()
2204 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, in LowerVAARG()
2210 MVT::i32, false, false, 0); in LowerVAARG()
2224 DAG.getConstant(12, MVT::i32), 8, false, true, false, in LowerVACOPY()
2242 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE()
2255 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
2315 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32); in LowerVASTART()
2316 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32); in LowerVASTART()
2341 MVT::i8, false, false, 0); in LowerVASTART()
2349 MachinePointerInfo(SV, nextOffset), MVT::i8, in LowerVASTART()
2377 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_PPC32_SVR4_Custom_Dummy()
2384 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, in CC_PPC32_SVR4_Custom_AlignArgRegs()
2385 MVT &LocVT, in CC_PPC32_SVR4_Custom_AlignArgRegs()
2411 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2412 MVT &LocVT, in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2473 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotAlignment()
2474 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotAlignment()
2475 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) in CalculateStackSlotAlignment()
2479 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1) in CalculateStackSlotAlignment()
2499 if (Flags.isSplit() && OrigVT != MVT::ppcf128) in CalculateStackSlotAlignment()
2543 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 || in CalculateStackSlotUsed()
2545 (HasQPX && (ArgVT == MVT::v4f32 || in CalculateStackSlotUsed()
2546 ArgVT == MVT::v4f64 || in CalculateStackSlotUsed()
2547 ArgVT == MVT::v4i1))) in CalculateStackSlotUsed()
2552 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotUsed()
2553 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotUsed()
2554 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) in CalculateStackSlotUsed()
2665 case MVT::i1: in LowerFormalArguments_32SVR4()
2666 case MVT::i32: in LowerFormalArguments_32SVR4()
2669 case MVT::f32: in LowerFormalArguments_32SVR4()
2672 case MVT::f64: in LowerFormalArguments_32SVR4()
2678 case MVT::v16i8: in LowerFormalArguments_32SVR4()
2679 case MVT::v8i16: in LowerFormalArguments_32SVR4()
2680 case MVT::v4i32: in LowerFormalArguments_32SVR4()
2683 case MVT::v4f32: in LowerFormalArguments_32SVR4()
2686 case MVT::v2f64: in LowerFormalArguments_32SVR4()
2687 case MVT::v2i64: in LowerFormalArguments_32SVR4()
2690 case MVT::v4f64: in LowerFormalArguments_32SVR4()
2693 case MVT::v4i1: in LowerFormalArguments_32SVR4()
2701 ValVT == MVT::i1 ? MVT::i32 : ValVT); in LowerFormalArguments_32SVR4()
2703 if (ValVT == MVT::i1) in LowerFormalArguments_32SVR4()
2704 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue); in LowerFormalArguments_32SVR4()
2771 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8; in LowerFormalArguments_32SVR4()
2808 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); in LowerFormalArguments_32SVR4()
2813 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, in LowerFormalArguments_32SVR4()
2820 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_32SVR4()
2832 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
2835 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
3000 EVT ObjType = (ObjSize == 1 ? MVT::i8 : in LowerFormalArguments_64SVR4()
3001 (ObjSize == 2 ? MVT::i16 : MVT::i32)); in LowerFormalArguments_64SVR4()
3050 case MVT::i1: in LowerFormalArguments_64SVR4()
3051 case MVT::i32: in LowerFormalArguments_64SVR4()
3052 case MVT::i64: in LowerFormalArguments_64SVR4()
3058 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
3060 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_64SVR4()
3075 case MVT::f32: in LowerFormalArguments_64SVR4()
3076 case MVT::f64: in LowerFormalArguments_64SVR4()
3083 if (ObjectVT == MVT::f32) in LowerFormalArguments_64SVR4()
3100 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
3102 if (ObjectVT == MVT::f32) { in LowerFormalArguments_64SVR4()
3104 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal, in LowerFormalArguments_64SVR4()
3105 DAG.getConstant(32, MVT::i32)); in LowerFormalArguments_64SVR4()
3106 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); in LowerFormalArguments_64SVR4()
3127 case MVT::v4f32: in LowerFormalArguments_64SVR4()
3128 case MVT::v4i32: in LowerFormalArguments_64SVR4()
3129 case MVT::v8i16: in LowerFormalArguments_64SVR4()
3130 case MVT::v16i8: in LowerFormalArguments_64SVR4()
3131 case MVT::v2f64: in LowerFormalArguments_64SVR4()
3132 case MVT::v2i64: in LowerFormalArguments_64SVR4()
3138 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ? in LowerFormalArguments_64SVR4()
3154 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && in LowerFormalArguments_64SVR4()
3158 case MVT::v4f64: in LowerFormalArguments_64SVR4()
3159 case MVT::v4i1: in LowerFormalArguments_64SVR4()
3162 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32; in LowerFormalArguments_64SVR4()
3166 case MVT::v4f64: RC = &PPC::QFRCRegClass; break; in LowerFormalArguments_64SVR4()
3167 case MVT::v4f32: RC = &PPC::QSRCRegClass; break; in LowerFormalArguments_64SVR4()
3239 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_64SVR4()
3259 bool isPPC64 = PtrVT == MVT::i64; in LowerFormalArguments_Darwin()
3315 case MVT::i1: in LowerFormalArguments_Darwin()
3316 case MVT::i32: in LowerFormalArguments_Darwin()
3317 case MVT::f32: in LowerFormalArguments_Darwin()
3320 case MVT::i64: // PPC64 in LowerFormalArguments_Darwin()
3321 case MVT::f64: in LowerFormalArguments_Darwin()
3326 case MVT::v4f32: in LowerFormalArguments_Darwin()
3327 case MVT::v4i32: in LowerFormalArguments_Darwin()
3328 case MVT::v8i16: in LowerFormalArguments_Darwin()
3329 case MVT::v16i8: in LowerFormalArguments_Darwin()
3362 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || in LowerFormalArguments_Darwin()
3363 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { in LowerFormalArguments_Darwin()
3401 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16; in LowerFormalArguments_Darwin()
3442 case MVT::i1: in LowerFormalArguments_Darwin()
3443 case MVT::i32: in LowerFormalArguments_Darwin()
3447 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); in LowerFormalArguments_Darwin()
3449 if (ObjectVT == MVT::i1) in LowerFormalArguments_Darwin()
3450 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal); in LowerFormalArguments_Darwin()
3462 case MVT::i64: // PPC64 in LowerFormalArguments_Darwin()
3465 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_Darwin()
3467 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_Darwin()
3481 case MVT::f32: in LowerFormalArguments_Darwin()
3482 case MVT::f64: in LowerFormalArguments_Darwin()
3493 if (ObjectVT == MVT::f32) in LowerFormalArguments_Darwin()
3507 case MVT::v4f32: in LowerFormalArguments_Darwin()
3508 case MVT::v4i32: in LowerFormalArguments_Darwin()
3509 case MVT::v8i16: in LowerFormalArguments_Darwin()
3510 case MVT::v16i8: in LowerFormalArguments_Darwin()
3605 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_Darwin()
3730 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
3760 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
3781 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
3809 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); in CreateCopyOfByValArgument()
3829 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerMemOpCallTo()
3831 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerMemOpCallTo()
3857 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2); in PrepareTailCall()
3896 NodeTys.push_back(MVT::Other); // Returns a chain in PrepareCall()
3897 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. in PrepareCall()
4001 if (LDChain.getValueType() == MVT::Glue) in PrepareCall()
4007 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI, in PrepareCall()
4012 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff); in PrepareCall()
4013 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr, in PrepareCall()
4018 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff); in PrepareCall()
4019 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC, in PrepareCall()
4045 NodeTys.push_back(MVT::Other); in PrepareCall()
4046 NodeTys.push_back(MVT::Glue); in PrepareCall()
4065 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); in PrepareCall()
4159 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); in FinishCall()
4187 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops); in FinishCall()
4217 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff); in FinishCall()
4331 MVT ArgVT = Outs[i].VT; in LowerCall_32SVR4()
4390 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_32SVR4()
4442 if (Arg.getValueType() == MVT::i1) in LowerCall_32SVR4()
4443 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg); in LowerCall_32SVR4()
4469 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32SVR4()
4483 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_32SVR4()
4596 case MVT::i1: in LowerCall_64SVR4()
4597 case MVT::i32: in LowerCall_64SVR4()
4598 case MVT::i64: in LowerCall_64SVR4()
4602 case MVT::v4i32: in LowerCall_64SVR4()
4603 case MVT::v8i16: in LowerCall_64SVR4()
4604 case MVT::v16i8: in LowerCall_64SVR4()
4605 case MVT::v2f64: in LowerCall_64SVR4()
4606 case MVT::v2i64: in LowerCall_64SVR4()
4610 case MVT::v4f32: in LowerCall_64SVR4()
4621 case MVT::f32: in LowerCall_64SVR4()
4622 case MVT::f64: in LowerCall_64SVR4()
4623 case MVT::v4f64: // QPX in LowerCall_64SVR4()
4624 case MVT::v4i1: // QPX in LowerCall_64SVR4()
4680 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerCall_64SVR4()
4725 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) { in LowerCall_64SVR4()
4728 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
4752 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); in LowerCall_64SVR4()
4849 case MVT::i1: in LowerCall_64SVR4()
4850 case MVT::i32: in LowerCall_64SVR4()
4851 case MVT::i64: in LowerCall_64SVR4()
4870 case MVT::f32: in LowerCall_64SVR4()
4871 case MVT::f64: { in LowerCall_64SVR4()
4901 if (Arg.getValueType() != MVT::f32) { in LowerCall_64SVR4()
4902 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); in LowerCall_64SVR4()
4906 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
4907 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
4913 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]); in LowerCall_64SVR4()
4914 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
4917 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerCall_64SVR4()
4921 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
4922 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
4924 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal, in LowerCall_64SVR4()
4925 DAG.getConstant(32, MVT::i32)); in LowerCall_64SVR4()
4940 if (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
4956 ArgOffset += (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
4963 case MVT::v4f32: in LowerCall_64SVR4()
4964 case MVT::v4i32: in LowerCall_64SVR4()
4965 case MVT::v8i16: in LowerCall_64SVR4()
4966 case MVT::v16i8: in LowerCall_64SVR4()
4967 case MVT::v2f64: in LowerCall_64SVR4()
4968 case MVT::v2i64: in LowerCall_64SVR4()
4985 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, in LowerCall_64SVR4()
4990 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 || in LowerCall_64SVR4()
4991 Arg.getSimpleValueType() == MVT::v2i64) ? in LowerCall_64SVR4()
5013 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 || in LowerCall_64SVR4()
5014 Arg.getSimpleValueType() == MVT::v2i64) ? in LowerCall_64SVR4()
5035 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 && in LowerCall_64SVR4()
5039 case MVT::v4f64: in LowerCall_64SVR4()
5040 case MVT::v4i1: { in LowerCall_64SVR4()
5041 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32; in LowerCall_64SVR4()
5049 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl, in LowerCall_64SVR4()
5094 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_64SVR4()
5104 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); in LowerCall_64SVR4()
5151 bool isPPC64 = PtrVT == MVT::i64; in LowerCall_Darwin()
5182 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in LowerCall_Darwin()
5183 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in LowerCall_Darwin()
5184 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) { in LowerCall_Darwin()
5241 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerCall_Darwin()
5243 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_Darwin()
5287 if (isPPC64 && Arg.getValueType() == MVT::i32) { in LowerCall_Darwin()
5290 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_Darwin()
5301 EVT VT = (Size==1) ? MVT::i8 : MVT::i16; in LowerCall_Darwin()
5351 case MVT::i1: in LowerCall_Darwin()
5352 case MVT::i32: in LowerCall_Darwin()
5353 case MVT::i64: in LowerCall_Darwin()
5355 if (Arg.getValueType() == MVT::i1) in LowerCall_Darwin()
5366 case MVT::f32: in LowerCall_Darwin()
5367 case MVT::f64: in LowerCall_Darwin()
5384 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ in LowerCall_Darwin()
5399 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && in LowerCall_Darwin()
5410 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; in LowerCall_Darwin()
5412 case MVT::v4f32: in LowerCall_Darwin()
5413 case MVT::v4i32: in LowerCall_Darwin()
5414 case MVT::v8i16: in LowerCall_Darwin()
5415 case MVT::v16i8: in LowerCall_Darwin()
5435 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, in LowerCall_Darwin()
5483 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || in LowerCall_Darwin()
5484 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { in LowerCall_Darwin()
5498 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_Darwin()
5585 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
5683 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); in LowerDYNAMIC_STACKALLOC()
5691 DAG.getVTList(MVT::i32, MVT::Other), in lowerEH_SJLJ_SETJMP()
5698 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other, in lowerEH_SJLJ_LONGJMP()
5706 assert(Op.getValueType() == MVT::i1 && in LowerLOAD()
5719 BasePtr, MVT::i8, MMO); in LowerLOAD()
5720 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD); in LowerLOAD()
5730 assert(Op.getOperand(1).getValueType() == MVT::i1 && in LowerSTORE()
5744 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO); in LowerSTORE()
5749 assert(Op.getValueType() == MVT::i1 && in LowerTRUNCATE()
5753 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1, in LowerTRUNCATE()
5789 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5790 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
5792 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5793 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
5795 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); in LowerSELECT_CC()
5801 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5802 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
5809 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5810 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
5812 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); in LowerSELECT_CC()
5822 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5823 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
5825 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5826 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
5828 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); in LowerSELECT_CC()
5832 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5833 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
5838 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5839 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
5844 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5845 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
5850 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
5851 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
5862 if (Src.getValueType() == MVT::f32) in LowerFP_TO_INTForReuse()
5863 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in LowerFP_TO_INTForReuse()
5868 case MVT::i32: in LowerFP_TO_INTForReuse()
5873 dl, MVT::f64, Src); in LowerFP_TO_INTForReuse()
5875 case MVT::i64: in LowerFP_TO_INTForReuse()
5880 dl, MVT::f64, Src); in LowerFP_TO_INTForReuse()
5885 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
5887 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64); in LowerFP_TO_INTForReuse()
5899 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO); in LowerFP_TO_INTForReuse()
5906 if (Op.getValueType() == MVT::i32 && !i32Stack) { in LowerFP_TO_INTForReuse()
5926 if (Src.getValueType() == MVT::f32) in LowerFP_TO_INTDirectMove()
5927 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in LowerFP_TO_INTDirectMove()
5932 case MVT::i32: in LowerFP_TO_INTDirectMove()
5937 dl, MVT::f64, Src); in LowerFP_TO_INTDirectMove()
5938 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp); in LowerFP_TO_INTDirectMove()
5940 case MVT::i64: in LowerFP_TO_INTDirectMove()
5945 dl, MVT::f64, Src); in LowerFP_TO_INTDirectMove()
5946 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp); in LowerFP_TO_INTDirectMove()
6025 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in spliceIntoChain()
6026 NewResChain, DAG.getUNDEF(MVT::Other)); in spliceIntoChain()
6040 assert((Op.getValueType() == MVT::f32 || in LowerINT_TO_FPDirectMove()
6041 Op.getValueType() == MVT::f64) && in LowerINT_TO_FPDirectMove()
6047 bool SinglePrec = Op.getValueType() == MVT::f32; in LowerINT_TO_FPDirectMove()
6048 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32; in LowerINT_TO_FPDirectMove()
6055 dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()
6056 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP); in LowerINT_TO_FPDirectMove()
6059 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()
6060 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP); in LowerINT_TO_FPDirectMove()
6070 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) { in LowerINT_TO_FP()
6071 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64) in LowerINT_TO_FP()
6078 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); in LowerINT_TO_FP()
6080 SDValue FPHalfs = DAG.getConstantFP(0.5, MVT::f64); in LowerINT_TO_FP()
6081 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, in LowerINT_TO_FP()
6084 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); in LowerINT_TO_FP()
6086 if (Op.getValueType() != MVT::v4f64) in LowerINT_TO_FP()
6093 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in LowerINT_TO_FP()
6096 if (Op.getOperand(0).getValueType() == MVT::i1) in LowerINT_TO_FP()
6111 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in LowerINT_TO_FP()
6116 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in LowerINT_TO_FP()
6117 ? MVT::f32 in LowerINT_TO_FP()
6118 : MVT::f64; in LowerINT_TO_FP()
6120 if (Op.getOperand(0).getValueType() == MVT::i64) { in LowerINT_TO_FP()
6132 if (Op.getValueType() == MVT::f32 && in LowerINT_TO_FP()
6142 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
6143 SINT, DAG.getConstant(2047, MVT::i64)); in LowerINT_TO_FP()
6144 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
6145 Round, DAG.getConstant(2047, MVT::i64)); in LowerINT_TO_FP()
6146 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); in LowerINT_TO_FP()
6147 Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
6148 Round, DAG.getConstant(-2048, MVT::i64)); in LowerINT_TO_FP()
6158 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, in LowerINT_TO_FP()
6159 SINT, DAG.getConstant(53, MVT::i32)); in LowerINT_TO_FP()
6160 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
6161 Cond, DAG.getConstant(1, MVT::i64)); in LowerINT_TO_FP()
6162 Cond = DAG.getSetCC(dl, MVT::i32, in LowerINT_TO_FP()
6163 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT); in LowerINT_TO_FP()
6165 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); in LowerINT_TO_FP()
6172 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) { in LowerINT_TO_FP()
6173 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false, in LowerINT_TO_FP()
6178 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) { in LowerINT_TO_FP()
6184 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
6185 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
6188 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { in LowerINT_TO_FP()
6194 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
6195 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
6201 SINT.getOperand(0).getValueType() == MVT::i32) { in LowerINT_TO_FP()
6213 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
6227 dl, DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
6228 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
6230 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); in LowerINT_TO_FP()
6234 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) in LowerINT_TO_FP()
6236 MVT::f32, FP, DAG.getIntPtrConstant(0)); in LowerINT_TO_FP()
6240 assert(Op.getOperand(0).getValueType() == MVT::i32 && in LowerINT_TO_FP()
6254 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI, in LowerINT_TO_FP()
6263 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
6278 dl, DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
6279 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
6289 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64, in LowerINT_TO_FP()
6298 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, in LowerINT_TO_FP()
6305 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) in LowerINT_TO_FP()
6306 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); in LowerINT_TO_FP()
6338 MVT::f64, // return register in LowerFLT_ROUNDS_()
6339 MVT::Glue // unused in this context in LowerFLT_ROUNDS_()
6352 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(), in LowerFLT_ROUNDS_()
6357 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFLT_ROUNDS_()
6358 CWD, DAG.getConstant(3, MVT::i32)); in LowerFLT_ROUNDS_()
6360 DAG.getNode(ISD::SRL, dl, MVT::i32, in LowerFLT_ROUNDS_()
6361 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFLT_ROUNDS_()
6362 DAG.getNode(ISD::XOR, dl, MVT::i32, in LowerFLT_ROUNDS_()
6363 CWD, DAG.getConstant(3, MVT::i32)), in LowerFLT_ROUNDS_()
6364 DAG.getConstant(3, MVT::i32)), in LowerFLT_ROUNDS_()
6365 DAG.getConstant(1, MVT::i32)); in LowerFLT_ROUNDS_()
6368 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); in LowerFLT_ROUNDS_()
6471 static const MVT VTys[] = { // canonical VT to use for each size. in BuildSplatI()
6472 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 in BuildSplatI()
6475 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; in BuildSplatI()
6484 SDValue Elt = DAG.getConstant(Val, MVT::i32); in BuildSplatI()
6495 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
6496 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
6498 DAG.getConstant(IID, MVT::i32), Op); in BuildIntrinsicOp()
6505 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
6506 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
6508 DAG.getConstant(IID, MVT::i32), LHS, RHS); in BuildIntrinsicOp()
6515 SDLoc dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
6516 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
6518 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); in BuildIntrinsicOp()
6527 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); in BuildVSLDOI()
6528 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); in BuildVSLDOI()
6533 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); in BuildVSLDOI()
6548 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) { in LowerBUILD_VECTOR()
6596 ValueVTs.push_back(MVT::v4i1); in LowerBUILD_VECTOR()
6597 ValueVTs.push_back(MVT::Other); // chain in LowerBUILD_VECTOR()
6601 dl, VTs, Ops, MVT::v4f32, in LowerBUILD_VECTOR()
6618 MVT::i32, false, false, 0)); in LowerBUILD_VECTOR()
6622 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue); in LowerBUILD_VECTOR()
6633 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in LowerBUILD_VECTOR()
6644 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, MVT::i32)); in LowerBUILD_VECTOR()
6648 ValueVTs.push_back(MVT::v4f64); in LowerBUILD_VECTOR()
6649 ValueVTs.push_back(MVT::Other); // chain in LowerBUILD_VECTOR()
6653 dl, VTs, Ops, MVT::v4i32, PtrInfo); in LowerBUILD_VECTOR()
6654 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64, in LowerBUILD_VECTOR()
6655 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, MVT::i32), in LowerBUILD_VECTOR()
6658 SDValue FPZeros = DAG.getConstantFP(0.0, MVT::f64); in LowerBUILD_VECTOR()
6659 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, in LowerBUILD_VECTOR()
6662 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ); in LowerBUILD_VECTOR()
6687 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { in LowerBUILD_VECTOR()
6688 SDValue Z = DAG.getConstant(0, MVT::i32); in LowerBUILD_VECTOR()
6689 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); in LowerBUILD_VECTOR()
6715 SDValue Elt = DAG.getConstant(SextVal, MVT::i32); in LowerBUILD_VECTOR()
6716 EVT VT = (SplatSize == 1 ? MVT::v16i8 : in LowerBUILD_VECTOR()
6717 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); in LowerBUILD_VECTOR()
6718 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32); in LowerBUILD_VECTOR()
6731 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); in LowerBUILD_VECTOR()
6738 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); in LowerBUILD_VECTOR()
6759 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
6770 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
6781 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
6793 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
6804 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
6809 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
6814 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
6893 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); in GeneratePerfectShuffle()
6894 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); in GeneratePerfectShuffle()
6895 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); in GeneratePerfectShuffle()
6921 DAG.getConstant(AlignIdx, MVT::i32)); in LowerVECTOR_SHUFFLE()
6933 DAG.getConstant(SplatIdx, MVT::i32)); in LowerVECTOR_SHUFFLE()
6946 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64, in LowerVECTOR_SHUFFLE()
6947 DAG.getConstant(idx, MVT::i32)); in LowerVECTOR_SHUFFLE()
7063 MVT::i32)); in LowerVECTOR_SHUFFLE()
7066 MVT::i32)); in LowerVECTOR_SHUFFLE()
7069 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, in LowerVECTOR_SHUFFLE()
7193 DAG.getConstant(CompareOpc, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
7201 DAG.getConstant(CompareOpc, MVT::i32) in LowerINTRINSIC_WO_CHAIN()
7203 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue }; in LowerINTRINSIC_WO_CHAIN()
7208 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
7209 DAG.getRegister(PPC::CR6, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
7232 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
7233 DAG.getConstant(8-(3-BitNo), MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
7235 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
7236 DAG.getConstant(1, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
7240 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
7241 DAG.getConstant(1, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
7251 if (Op.getValueType() == MVT::v2i64) { in LowerSIGN_EXTEND_INREG()
7253 if (ExtVT != MVT::v2i32) { in LowerSIGN_EXTEND_INREG()
7254 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)); in LowerSIGN_EXTEND_INREG()
7255 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op, in LowerSIGN_EXTEND_INREG()
7258 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op); in LowerSIGN_EXTEND_INREG()
7259 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op, in LowerSIGN_EXTEND_INREG()
7260 DAG.getValueType(MVT::v2i32)); in LowerSIGN_EXTEND_INREG()
7292 assert(N->getOperand(0).getValueType() == MVT::v4i1 && in LowerEXTRACT_VECTOR_ELT()
7303 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); in LowerEXTRACT_VECTOR_ELT()
7307 SDValue FPHalfs = DAG.getConstantFP(0.5, MVT::f64); in LowerEXTRACT_VECTOR_ELT()
7308 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, in LowerEXTRACT_VECTOR_ELT()
7311 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); in LowerEXTRACT_VECTOR_ELT()
7314 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64, in LowerEXTRACT_VECTOR_ELT()
7315 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, MVT::i32), in LowerEXTRACT_VECTOR_ELT()
7327 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, MVT::i32)); in LowerEXTRACT_VECTOR_ELT()
7332 ValueVTs.push_back(MVT::Other); // chain in LowerEXTRACT_VECTOR_ELT()
7336 dl, VTs, Ops, MVT::v4i32, PtrInfo); in LowerEXTRACT_VECTOR_ELT()
7343 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx, in LowerEXTRACT_VECTOR_ELT()
7350 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal); in LowerEXTRACT_VECTOR_ELT()
7361 if (Op.getValueType() == MVT::v4f64 || in LowerVectorLoad()
7362 Op.getValueType() == MVT::v4f32) { in LowerVectorLoad()
7407 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in LowerVectorLoad()
7420 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower"); in LowerVectorLoad()
7432 dl, MVT::i32, LoadChain, Idx, in LowerVectorLoad()
7434 MVT::i8 /* memory type */, in LowerVectorLoad()
7441 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains); in LowerVectorLoad()
7442 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts); in LowerVectorLoad()
7457 if (Value.getValueType() == MVT::v4f64 || in LowerVectorStore()
7458 Value.getValueType() == MVT::v4f32) { in LowerVectorStore()
7501 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in LowerVectorStore()
7512 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower"); in LowerVectorStore()
7517 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value); in LowerVectorStore()
7521 SDValue FPHalfs = DAG.getConstantFP(0.5, MVT::f64); in LowerVectorStore()
7522 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, in LowerVectorStore()
7525 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs); in LowerVectorStore()
7528 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64, in LowerVectorStore()
7529 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, MVT::i32), in LowerVectorStore()
7540 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, MVT::i32)); in LowerVectorStore()
7545 ValueVTs.push_back(MVT::Other); // chain in LowerVectorStore()
7549 dl, VTs, Ops, MVT::v4i32, PtrInfo); in LowerVectorStore()
7558 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx, in LowerVectorStore()
7564 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in LowerVectorStore()
7573 MVT::i8 /* memory type */, in LowerVectorStore()
7578 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in LowerVectorStore()
7585 if (Op.getValueType() == MVT::v4i32) { in LowerMUL()
7588 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); in LowerMUL()
7589 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. in LowerMUL()
7595 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); in LowerMUL()
7596 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); in LowerMUL()
7597 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); in LowerMUL()
7602 LHS, RHS, DAG, dl, MVT::v4i32); in LowerMUL()
7605 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); in LowerMUL()
7609 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); in LowerMUL()
7610 } else if (Op.getValueType() == MVT::v8i16) { in LowerMUL()
7613 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); in LowerMUL()
7617 } else if (Op.getValueType() == MVT::v16i8) { in LowerMUL()
7623 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
7624 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); in LowerMUL()
7628 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
7629 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); in LowerMUL()
7646 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops); in LowerMUL()
7648 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); in LowerMUL()
7725 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); in ReplaceNodeResults()
7738 assert(N->getValueType(0) == MVT::i1 && in ReplaceNodeResults()
7741 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); in ReplaceNodeResults()
7755 if (VT == MVT::i64) { in ReplaceNodeResults()
7764 assert(N->getValueType(0) == MVT::ppcf128); in ReplaceNodeResults()
7765 assert(N->getOperand(0).getValueType() == MVT::ppcf128); in ReplaceNodeResults()
7767 MVT::f64, N->getOperand(0), in ReplaceNodeResults()
7770 MVT::f64, N->getOperand(0), in ReplaceNodeResults()
7774 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi); in ReplaceNodeResults()
7778 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, in ReplaceNodeResults()
7785 if (N->getOperand(0).getValueType() == MVT::ppcf128) in ReplaceNodeResults()
8066 assert(RC->hasType(MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()
8070 MVT PVT = getPointerTy(); in emitEHSjLjSetJmp()
8071 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjSetJmp()
8208 MVT PVT = getPointerTy(); in emitEHSjLjLongJmp()
8209 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjLongJmp()
8213 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in emitEHSjLjLongJmp()
8216 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; in emitEHSjLjLongJmp()
8217 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; in emitEHSjLjLongJmp()
8219 (PVT == MVT::i64) in emitEHSjLjLongJmp()
8238 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
8250 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
8262 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
8274 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
8286 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
8297 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); in emitEHSjLjLongJmp()
8298 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); in emitEHSjLjLongJmp()
8856 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getRsqrtEstimate()
8857 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getRsqrtEstimate()
8858 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRsqrtEstimate()
8859 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRsqrtEstimate()
8860 (VT == MVT::v4f32 && Subtarget.hasQPX()) || in getRsqrtEstimate()
8861 (VT == MVT::v4f64 && Subtarget.hasQPX())) { in getRsqrtEstimate()
8867 if (VT.getScalarType() == MVT::f64) in getRsqrtEstimate()
8879 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
8880 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
8881 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
8882 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRecipEstimate()
8883 (VT == MVT::v4f32 && Subtarget.hasQPX()) || in getRecipEstimate()
8884 (VT == MVT::v4f64 && Subtarget.hasQPX())) { in getRecipEstimate()
8890 if (VT.getScalarType() == MVT::f64) in getRecipEstimate()
8972 VT = MVT::v4f64; in isConsecutiveLS()
8976 VT = MVT::v4f32; in isConsecutiveLS()
8980 VT = MVT::v2f64; in isConsecutiveLS()
8984 VT = MVT::v2f32; in isConsecutiveLS()
8991 VT = MVT::v4i32; in isConsecutiveLS()
8994 VT = MVT::v2f64; in isConsecutiveLS()
8997 VT = MVT::i8; in isConsecutiveLS()
9000 VT = MVT::i16; in isConsecutiveLS()
9003 VT = MVT::i32; in isConsecutiveLS()
9016 VT = MVT::v4f64; in isConsecutiveLS()
9020 VT = MVT::v4f32; in isConsecutiveLS()
9024 VT = MVT::v2f64; in isConsecutiveLS()
9028 VT = MVT::v2f32; in isConsecutiveLS()
9035 VT = MVT::v4i32; in isConsecutiveLS()
9038 VT = MVT::v2f64; in isConsecutiveLS()
9041 VT = MVT::i8; in isConsecutiveLS()
9044 VT = MVT::i16; in isConsecutiveLS()
9047 VT = MVT::i32; in isConsecutiveLS()
9141 N->getValueType(0) != MVT::i1) in DAGCombineTruncBoolExt()
9144 if (N->getOperand(0).getValueType() != MVT::i32 && in DAGCombineTruncBoolExt()
9145 N->getOperand(0).getValueType() != MVT::i64) in DAGCombineTruncBoolExt()
9219 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
9250 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
9349 PromOp.getOperand(0).getValueType() != MVT::i1) { in DAGCombineTruncBoolExt()
9357 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue); in DAGCombineTruncBoolExt()
9371 PromOp.getOperand(C).getValueType() != MVT::i1) || in DAGCombineTruncBoolExt()
9373 PromOp.getOperand(C+1).getValueType() != MVT::i1)) { in DAGCombineTruncBoolExt()
9388 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]); in DAGCombineTruncBoolExt()
9391 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops)); in DAGCombineTruncBoolExt()
9422 if (N->getValueType(0) != MVT::i32 && in DAGCombineExtBoolTrunc()
9423 N->getValueType(0) != MVT::i64) in DAGCombineExtBoolTrunc()
9426 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
9427 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
9695 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in combineFPToIntToFP()
9697 if (Op.getOperand(0).getValueType() == MVT::i1) in combineFPToIntToFP()
9704 if (Op.getOperand(0).getValueType() == MVT::i32) in combineFPToIntToFP()
9712 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
9717 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
9718 ? MVT::f32 in combineFPToIntToFP()
9719 : MVT::f64; in combineFPToIntToFP()
9727 if (Src.getValueType() == MVT::f32) { in combineFPToIntToFP()
9728 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in combineFPToIntToFP()
9736 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src); in combineFPToIntToFP()
9739 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
9741 MVT::f32, FP, DAG.getIntPtrConstant(0)); in combineFPToIntToFP()
9785 MVT VecTy = N->getValueType(0).getSimpleVT(); in expandVSXLoadForLE()
9788 DAG.getVTList(VecTy, MVT::Other), in expandVSXLoadForLE()
9793 DAG.getVTList(VecTy, MVT::Other), Chain, Load); in expandVSXLoadForLE()
9837 MVT VecTy = Src.getValueType().getSimpleVT(); in expandVSXStoreForLE()
9839 DAG.getVTList(VecTy, MVT::Other), Chain, Src); in expandVSXStoreForLE()
9844 DAG.getVTList(MVT::Other), in expandVSXStoreForLE()
9890 N->getOperand(1).getValueType() == MVT::i32 && in PerformDAGCombine()
9891 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { in PerformDAGCombine()
9893 if (Val.getValueType() == MVT::f32) { in PerformDAGCombine()
9894 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); in PerformDAGCombine()
9897 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); in PerformDAGCombine()
9906 DAG.getVTList(MVT::Other), Ops, in PerformDAGCombine()
9917 (N->getOperand(1).getValueType() == MVT::i32 || in PerformDAGCombine()
9918 N->getOperand(1).getValueType() == MVT::i16 || in PerformDAGCombine()
9920 N->getOperand(1).getValueType() == MVT::i64))) { in PerformDAGCombine()
9923 if (BSwapOp.getValueType() == MVT::i16) in PerformDAGCombine()
9924 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); in PerformDAGCombine()
9931 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), in PerformDAGCombine()
9939 MVT StoreVT = VT.getSimpleVT(); in PerformDAGCombine()
9941 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 || in PerformDAGCombine()
9942 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32)) in PerformDAGCombine()
9953 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine()
9955 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
9956 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()
9968 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 || in PerformDAGCombine()
9969 VT == MVT::v4i32 || VT == MVT::v4f32)) || in PerformDAGCombine()
9970 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) && in PerformDAGCombine()
10003 MVT PermCntlTy, PermTy, LDTy; in PerformDAGCombine()
10009 PermCntlTy = MVT::v16i8; in PerformDAGCombine()
10010 PermTy = MVT::v4i32; in PerformDAGCombine()
10011 LDTy = MVT::v4i32; in PerformDAGCombine()
10013 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld : in PerformDAGCombine()
10015 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd : in PerformDAGCombine()
10018 PermCntlTy = MVT::v4f64; in PerformDAGCombine()
10019 PermTy = MVT::v4f64; in PerformDAGCombine()
10040 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
10069 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
10072 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in PerformDAGCombine()
10092 DAG.getTargetConstant(1, MVT::i64)); in PerformDAGCombine()
10191 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || in PerformDAGCombine()
10193 N->getValueType(0) == MVT::i64))) { in PerformDAGCombine()
10204 DAG.getVTList(N->getValueType(0) == MVT::i64 ? in PerformDAGCombine()
10205 MVT::i64 : MVT::i32, MVT::Other), in PerformDAGCombine()
10210 if (N->getValueType(0) == MVT::i16) in PerformDAGCombine()
10211 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); in PerformDAGCombine()
10291 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other, in PerformDAGCombine()
10332 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other, in PerformDAGCombine()
10351 return DAG.getNode(ISD::BR, dl, MVT::Other, in PerformDAGCombine()
10361 DAG.getConstant(CompareOpc, MVT::i32) in PerformDAGCombine()
10363 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue }; in PerformDAGCombine()
10384 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), in PerformDAGCombine()
10385 DAG.getConstant(CompOpc, MVT::i32), in PerformDAGCombine()
10386 DAG.getRegister(PPC::CR6, MVT::i32), in PerformDAGCombine()
10402 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
10404 if ((VT != MVT::i32 && VT != MVT::i64) || in BuildSDIVPow2()
10442 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) in computeKnownBitsForTargetNode()
10594 MVT VT) const { in getRegForInlineAsmConstraint()
10599 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
10603 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
10607 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
10609 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
10611 if (VT == MVT::v4f64 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10613 if (VT == MVT::v4f32 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10617 if (VT == MVT::v4f64 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10619 if (VT == MVT::v4f32 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10643 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
10684 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative in LowerAsmOperandForConstraint()
10794 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
10813 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR()
10843 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) || in getRegisterByName()
10844 (!isPPC64 && VT != MVT::i32)) in getRegisterByName()
10847 bool is64Bit = isPPC64 && VT == MVT::i64; in getRegisterByName()
10887 VT = MVT::i8; in getTgtMemIntrinsic()
10890 VT = MVT::i16; in getTgtMemIntrinsic()
10893 VT = MVT::i32; in getTgtMemIntrinsic()
10896 VT = MVT::v2f64; in getTgtMemIntrinsic()
10899 VT = MVT::v4f64; in getTgtMemIntrinsic()
10902 VT = MVT::v4f32; in getTgtMemIntrinsic()
10905 VT = MVT::v2f64; in getTgtMemIntrinsic()
10908 VT = MVT::v2f32; in getTgtMemIntrinsic()
10911 VT = MVT::v4i32; in getTgtMemIntrinsic()
10935 VT = MVT::v4f64; in getTgtMemIntrinsic()
10938 VT = MVT::v4f32; in getTgtMemIntrinsic()
10941 VT = MVT::v2f64; in getTgtMemIntrinsic()
10944 VT = MVT::v2f32; in getTgtMemIntrinsic()
10947 VT = MVT::v4i32; in getTgtMemIntrinsic()
10977 VT = MVT::i8; in getTgtMemIntrinsic()
10980 VT = MVT::i16; in getTgtMemIntrinsic()
10983 VT = MVT::i32; in getTgtMemIntrinsic()
10986 VT = MVT::v2f64; in getTgtMemIntrinsic()
10989 VT = MVT::v4f64; in getTgtMemIntrinsic()
10992 VT = MVT::v4f32; in getTgtMemIntrinsic()
10995 VT = MVT::v2f64; in getTgtMemIntrinsic()
10998 VT = MVT::v2f32; in getTgtMemIntrinsic()
11001 VT = MVT::v4i32; in getTgtMemIntrinsic()
11024 VT = MVT::v4f64; in getTgtMemIntrinsic()
11027 VT = MVT::v4f32; in getTgtMemIntrinsic()
11030 VT = MVT::v2f64; in getTgtMemIntrinsic()
11033 VT = MVT::v2f32; in getTgtMemIntrinsic()
11036 VT = MVT::v4i32; in getTgtMemIntrinsic()
11081 return MVT::v4f64; in getOptimalMemOpType()
11089 return MVT::v4i32; in getOptimalMemOpType()
11093 return MVT::i64; in getOptimalMemOpType()
11096 return MVT::i32; in getOptimalMemOpType()
11132 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 || in isZExtFree()
11133 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
11178 if (VT != MVT::v2f64 && VT != MVT::v2i64 && in allowsMisalignedMemoryAccesses()
11179 VT != MVT::v4f32 && VT != MVT::v4i32) in allowsMisalignedMemoryAccesses()
11186 if (VT == MVT::ppcf128) in allowsMisalignedMemoryAccesses()
11202 case MVT::f32: in isFMAFasterThanFMulAndFAdd()
11203 case MVT::f64: in isFMAFasterThanFMulAndFAdd()
11228 if (VT == MVT::v2i64) in shouldExpandBuildVectorWithShuffles()
11232 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1) in shouldExpandBuildVectorWithShuffles()