153       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();  in runOnMachineFunction()  local
155         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));  in runOnMachineFunction()
182   const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();  in EmitProgramInfoR600()  local
206     switch (MFI->getShaderType()) {  in EmitProgramInfoR600()
215     switch (MFI->getShaderType()) {  in EmitProgramInfoR600()
226                            S_STACK_SIZE(MFI->StackSize), 4);  in EmitProgramInfoR600()
230   if (MFI->getShaderType() == ShaderType::COMPUTE) {  in EmitProgramInfoR600()
232     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);  in EmitProgramInfoR600()
239   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();  in getSIProgramInfo()  local
375   unsigned LDSSpillSize = MFI->LDSWaveSpillSize *  in getSIProgramInfo()
376                           MFI->getMaximumWorkGroupSize(MF);  in getSIProgramInfo()
378   ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;  in getSIProgramInfo()
403       S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |  in getSIProgramInfo()
425   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();  in EmitProgramInfoSI()  local
426   unsigned RsrcReg = getRsrcReg(MFI->getShaderType());  in EmitProgramInfoSI()
428   if (MFI->getShaderType() == ShaderType::COMPUTE) {  in EmitProgramInfoSI()
445     if (STM.isVGPRSpillingEnabled(MFI)) {  in EmitProgramInfoSI()
451   if (MFI->getShaderType() == ShaderType::PIXEL) {  in EmitProgramInfoSI()
455     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);  in EmitProgramInfoSI()
461   const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();  in EmitAmdKernelCodeT()  local
498   header.kernarg_segment_byte_size = MFI->ABIArgOffset;  in EmitAmdKernelCodeT()