Lines Matching refs:getRegClass
173 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) { in printRegOperand()
176 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) { in printRegOperand()
179 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) { in printRegOperand()
182 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) { in printRegOperand()
185 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) { in printRegOperand()
188 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) { in printRegOperand()
191 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) { in printRegOperand()
194 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) { in printRegOperand()
197 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) { in printRegOperand()
200 } else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) { in printRegOperand()
203 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) { in printRegOperand()
308 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID); in printOperand()
329 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass); in printOperand()