Lines Matching refs:OpName
76 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0)) in copyPhysReg()
154 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) == -1; in isLDSNoRetInstr()
158 return isLDSInstr(Opcode) && getOperandIdx(Opcode, AMDGPU::OpName::dst) != -1; in isLDSRetInstr()
260 AMDGPU::OpName::src0, in getSrcIdx()
261 AMDGPU::OpName::src1, in getSrcIdx()
262 AMDGPU::OpName::src2 in getSrcIdx()
271 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel}, in getSelIdx()
272 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}, in getSelIdx()
273 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel}, in getSelIdx()
274 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X}, in getSelIdx()
275 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y}, in getSelIdx()
276 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z}, in getSelIdx()
277 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W}, in getSelIdx()
278 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X}, in getSelIdx()
279 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y}, in getSelIdx()
280 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z}, in getSelIdx()
281 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W} in getSelIdx()
298 {AMDGPU::OpName::src0_X, AMDGPU::OpName::src0_sel_X}, in getSrcs()
299 {AMDGPU::OpName::src0_Y, AMDGPU::OpName::src0_sel_Y}, in getSrcs()
300 {AMDGPU::OpName::src0_Z, AMDGPU::OpName::src0_sel_Z}, in getSrcs()
301 {AMDGPU::OpName::src0_W, AMDGPU::OpName::src0_sel_W}, in getSrcs()
302 {AMDGPU::OpName::src1_X, AMDGPU::OpName::src1_sel_X}, in getSrcs()
303 {AMDGPU::OpName::src1_Y, AMDGPU::OpName::src1_sel_Y}, in getSrcs()
304 {AMDGPU::OpName::src1_Z, AMDGPU::OpName::src1_sel_Z}, in getSrcs()
305 {AMDGPU::OpName::src1_W, AMDGPU::OpName::src1_sel_W}, in getSrcs()
324 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel}, in getSrcs()
325 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_sel}, in getSrcs()
326 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_sel}, in getSrcs()
343 getOperandIdx(MI->getOpcode(), AMDGPU::OpName::literal)).getImm(); in getSrcs()
562 AMDGPU::OpName::bank_swizzle); in fitsReadPortLimitations()
1020 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X)) in PredicateInstruction()
1022 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y)) in PredicateInstruction()
1024 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z)) in PredicateInstruction()
1026 MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W)) in PredicateInstruction()
1133 setImmOperand(MOVA, AMDGPU::OpName::write, 0); in buildIndirectWrite()
1139 setImmOperand(Mov, AMDGPU::OpName::dst_rel, 1); in buildIndirectWrite()
1166 setImmOperand(MOVA, AMDGPU::OpName::write, 0); in buildIndirectRead()
1172 setImmOperand(Mov, AMDGPU::OpName::src0_rel, 1); in buildIndirectRead()
1236 OPERAND_CASE(AMDGPU::OpName::update_exec_mask) in getSlotedOps()
1237 OPERAND_CASE(AMDGPU::OpName::update_pred) in getSlotedOps()
1238 OPERAND_CASE(AMDGPU::OpName::write) in getSlotedOps()
1239 OPERAND_CASE(AMDGPU::OpName::omod) in getSlotedOps()
1240 OPERAND_CASE(AMDGPU::OpName::dst_rel) in getSlotedOps()
1241 OPERAND_CASE(AMDGPU::OpName::clamp) in getSlotedOps()
1242 OPERAND_CASE(AMDGPU::OpName::src0) in getSlotedOps()
1243 OPERAND_CASE(AMDGPU::OpName::src0_neg) in getSlotedOps()
1244 OPERAND_CASE(AMDGPU::OpName::src0_rel) in getSlotedOps()
1245 OPERAND_CASE(AMDGPU::OpName::src0_abs) in getSlotedOps()
1246 OPERAND_CASE(AMDGPU::OpName::src0_sel) in getSlotedOps()
1247 OPERAND_CASE(AMDGPU::OpName::src1) in getSlotedOps()
1248 OPERAND_CASE(AMDGPU::OpName::src1_neg) in getSlotedOps()
1249 OPERAND_CASE(AMDGPU::OpName::src1_rel) in getSlotedOps()
1250 OPERAND_CASE(AMDGPU::OpName::src1_abs) in getSlotedOps()
1251 OPERAND_CASE(AMDGPU::OpName::src1_sel) in getSlotedOps()
1252 OPERAND_CASE(AMDGPU::OpName::pred_sel) in getSlotedOps()
1271 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src0, Slot))); in buildSlotOfVectorInstruction()
1273 getOperandIdx(MI->getOpcode(), getSlotedOps(AMDGPU::OpName::src1, Slot))); in buildSlotOfVectorInstruction()
1277 AMDGPU::OpName::update_exec_mask, in buildSlotOfVectorInstruction()
1278 AMDGPU::OpName::update_pred, in buildSlotOfVectorInstruction()
1279 AMDGPU::OpName::write, in buildSlotOfVectorInstruction()
1280 AMDGPU::OpName::omod, in buildSlotOfVectorInstruction()
1281 AMDGPU::OpName::dst_rel, in buildSlotOfVectorInstruction()
1282 AMDGPU::OpName::clamp, in buildSlotOfVectorInstruction()
1283 AMDGPU::OpName::src0_neg, in buildSlotOfVectorInstruction()
1284 AMDGPU::OpName::src0_rel, in buildSlotOfVectorInstruction()
1285 AMDGPU::OpName::src0_abs, in buildSlotOfVectorInstruction()
1286 AMDGPU::OpName::src0_sel, in buildSlotOfVectorInstruction()
1287 AMDGPU::OpName::src1_neg, in buildSlotOfVectorInstruction()
1288 AMDGPU::OpName::src1_rel, in buildSlotOfVectorInstruction()
1289 AMDGPU::OpName::src1_abs, in buildSlotOfVectorInstruction()
1290 AMDGPU::OpName::src1_sel, in buildSlotOfVectorInstruction()
1294 getSlotedOps(AMDGPU::OpName::pred_sel, Slot))); in buildSlotOfVectorInstruction()
1295 MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel)) in buildSlotOfVectorInstruction()
1314 setImmOperand(MovImm, AMDGPU::OpName::literal, Imm); in buildMovImm()
1360 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::clamp); in getFlagOp()
1363 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::write); in getFlagOp()
1367 FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::last); in getFlagOp()
1371 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_neg); break; in getFlagOp()
1372 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_neg); break; in getFlagOp()
1373 case 2: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src2_neg); break; in getFlagOp()
1382 case 0: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src0_abs); break; in getFlagOp()
1383 case 1: FlagIndex = getOperandIdx(*MI, AMDGPU::OpName::src1_abs); break; in getFlagOp()