Lines Matching refs:BuildMI
338 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) in copyPhysReg()
345 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC) in copyPhysReg()
350 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_I32_e32), AMDGPU::VCC) in copyPhysReg()
359 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) in copyPhysReg()
381 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in copyPhysReg()
419 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, in copyPhysReg()
499 BuildMI(MBB, MI, DL, get(Opcode)) in storeRegToStackSlot()
510 BuildMI(MBB, MI, DL, get(AMDGPU::KILL)) in storeRegToStackSlot()
547 BuildMI(MBB, MI, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
558 BuildMI(MBB, MI, DL, get(AMDGPU::IMPLICIT_DEF), DestReg); in loadRegFromStackSlot()
604 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0) in calculateLDSSpillAddress()
607 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1) in calculateLDSSpillAddress()
612 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1) in calculateLDSSpillAddress()
616 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg) in calculateLDSSpillAddress()
620 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg) in calculateLDSSpillAddress()
625 BuildMI(Entry, Insert, DL, get(AMDGPU::V_ADD_I32_e32), TIDReg) in calculateLDSSpillAddress()
630 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64), in calculateLDSSpillAddress()
635 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64), in calculateLDSSpillAddress()
641 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32), in calculateLDSSpillAddress()
650 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e32), TmpReg) in calculateLDSSpillAddress()
666 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP)) in insertNOPs()
682 BuildMI(MBB, MI, DL, get(AMDGPU::S_GETPC_B64), Reg); in expandPostRAPseudo()
685 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADD_U32), RegLo) in expandPostRAPseudo()
689 BuildMI(MBB, MI, DL, get(AMDGPU::S_ADDC_U32), RegHi) in expandPostRAPseudo()
712 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
715 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
720 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo) in expandPostRAPseudo()
723 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
739 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstLo) in expandPostRAPseudo()
743 BuildMI(MBB, MI, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstHi) in expandPostRAPseudo()
869 return BuildMI(*MBB, I, MBB->findDebugLoc(I), get(AMDGPU::V_MOV_B32_e32), in buildMovInstr()
1487 BuildMI(*MI->getParent(), I, DL, get(Opcode), Reg) in legalizeOpWithMove()
1511 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg) in buildExtractSubReg()
1514 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) in buildExtractSubReg()
1553 MachineInstr *Lo = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), in split64BitImm()
1556 MachineInstr *Hi = BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), in split64BitImm()
1560 BuildMI(*MBB, MI, DL, get(TargetOpcode::REG_SEQUENCE), Dst) in split64BitImm()
1751 BuildMI(*InsertBB, Insert, MI->getDebugLoc(), in legalizeOperands()
1768 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::COPY), NewSrc0) in legalizeOperands()
1810 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B64), in legalizeOperands()
1815 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), in legalizeOperands()
1820 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), in legalizeOperands()
1825 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), in legalizeOperands()
1845 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADD_I32_e32), in legalizeOperands()
1852 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_ADDC_U32_e32), in legalizeOperands()
1869 BuildMI(MBB, MI, MI->getDebugLoc(), get(Addr64Opcode)) in legalizeOperands()
1891 BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), in legalizeOperands()
1933 Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo) in splitSMRD()
1942 BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR) in splitSMRD()
1944 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi) in splitSMRD()
1949 Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi) in splitSMRD()
1957 Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo) in splitSMRD()
1961 BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR) in splitSMRD()
1964 Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp)) in splitSMRD()
1992 BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE)) in splitSMRD()
2027 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), in moveSMRDToVALU()
2031 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), in moveSMRDToVALU()
2045 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord1) in moveSMRDToVALU()
2047 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord2) in moveSMRDToVALU()
2049 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_MOV_B32), DWord3) in moveSMRDToVALU()
2051 BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::REG_SEQUENCE), SRsrc) in moveSMRDToVALU()
2129 MachineInstr *Copy = BuildMI(*MBB, Inst, DL, get(TargetOpcode::COPY)) in moveToVALU()
2351 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitUnaryOp()
2358 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitUnaryOp()
2362 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitUnaryOp()
2411 MachineInstr *LoHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
2421 MachineInstr *HiHalf = BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
2426 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg) in splitScalar64BitBinaryOp()
2466 MachineInstr *First = BuildMI(MBB, MII, DL, InstDesc, MidReg) in splitScalar64BitBCNT()
2470 MachineInstr *Second = BuildMI(MBB, MII, DL, InstDesc, ResultReg) in splitScalar64BitBCNT()
2505 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo) in splitScalar64BitBFE()
2510 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi) in splitScalar64BitBFE()
2514 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
2528 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg) in splitScalar64BitBFE()
2532 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
2636 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_DST_V1)) in buildIndirectWrite()
2654 return BuildMI(*MBB, I, DL, get(AMDGPU::SI_INDIRECT_SRC)) in buildIndirectRead()