Lines Matching refs:add
70 (add (sequence "SGPR%u", 0, 101))>;
74 [(add (decimate (trunc SGPR_32, 101), 2)),
75 (add (decimate (shl SGPR_32, 1), 2))]>;
79 [(add (decimate (trunc SGPR_32, 99), 4)),
80 (add (decimate (shl SGPR_32, 1), 4)),
81 (add (decimate (shl SGPR_32, 2), 4)),
82 (add (decimate (shl SGPR_32, 3), 4))]>;
86 [(add (decimate (trunc SGPR_32, 95), 4)),
87 (add (decimate (shl SGPR_32, 1), 4)),
88 (add (decimate (shl SGPR_32, 2), 4)),
89 (add (decimate (shl SGPR_32, 3), 4)),
90 (add (decimate (shl SGPR_32, 4), 4)),
91 (add (decimate (shl SGPR_32, 5), 4)),
92 (add (decimate (shl SGPR_32, 6), 4)),
93 (add (decimate (shl SGPR_32, 7), 4))]>;
98 [(add (decimate (trunc SGPR_32, 87), 4)),
99 (add (decimate (shl SGPR_32, 1), 4)),
100 (add (decimate (shl SGPR_32, 2), 4)),
101 (add (decimate (shl SGPR_32, 3), 4)),
102 (add (decimate (shl SGPR_32, 4), 4)),
103 (add (decimate (shl SGPR_32, 5), 4)),
104 (add (decimate (shl SGPR_32, 6), 4)),
105 (add (decimate (shl SGPR_32, 7), 4)),
106 (add (decimate (shl SGPR_32, 8), 4)),
107 (add (decimate (shl SGPR_32, 9), 4)),
108 (add (decimate (shl SGPR_32, 10), 4)),
109 (add (decimate (shl SGPR_32, 11), 4)),
110 (add (decimate (shl SGPR_32, 12), 4)),
111 (add (decimate (shl SGPR_32, 13), 4)),
112 (add (decimate (shl SGPR_32, 14), 4)),
113 (add (decimate (shl SGPR_32, 15), 4))]>;
117 (add (sequence "VGPR%u", 0, 255))>;
121 [(add (trunc VGPR_32, 255)),
122 (add (shl VGPR_32, 1))]>;
126 [(add (trunc VGPR_32, 254)),
127 (add (shl VGPR_32, 1)),
128 (add (shl VGPR_32, 2))]>;
132 [(add (trunc VGPR_32, 253)),
133 (add (shl VGPR_32, 1)),
134 (add (shl VGPR_32, 2)),
135 (add (shl VGPR_32, 3))]>;
139 [(add (trunc VGPR_32, 249)),
140 (add (shl VGPR_32, 1)),
141 (add (shl VGPR_32, 2)),
142 (add (shl VGPR_32, 3)),
143 (add (shl VGPR_32, 4)),
144 (add (shl VGPR_32, 5)),
145 (add (shl VGPR_32, 6)),
146 (add (shl VGPR_32, 7))]>;
151 [(add (trunc VGPR_32, 241)),
152 (add (shl VGPR_32, 1)),
153 (add (shl VGPR_32, 2)),
154 (add (shl VGPR_32, 3)),
155 (add (shl VGPR_32, 4)),
156 (add (shl VGPR_32, 5)),
157 (add (shl VGPR_32, 6)),
158 (add (shl VGPR_32, 7)),
159 (add (shl VGPR_32, 8)),
160 (add (shl VGPR_32, 9)),
161 (add (shl VGPR_32, 10)),
162 (add (shl VGPR_32, 11)),
163 (add (shl VGPR_32, 12)),
164 (add (shl VGPR_32, 13)),
165 (add (shl VGPR_32, 14)),
166 (add (shl VGPR_32, 15))]>;
178 def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> {
183 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
184 def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
185 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
189 (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
192 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 64, (add SGPR_64Regs)>;
195 (add SGPR_64, VCCReg, EXECReg, FLAT_SCR)
198 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8], 128, (add SGPR_128)>;
200 def SReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add SGPR_256)>;
202 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 512, (add SGPR_512)>;
205 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 64, (add VGPR_64)>;
207 def VReg_96 : RegisterClass<"AMDGPU", [untyped], 96, (add VGPR_96)> {
211 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128, (add VGPR_128)>;
213 def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256)>;
215 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
217 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
255 def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>;
257 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 64, (add VReg_64, SReg_64)>;