Lines Matching refs:DCI
12769 DAGCombinerInfo &DCI, in getRsqrtEstimate() argument
12792 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op); in getRsqrtEstimate()
12800 DAGCombinerInfo &DCI, in getRecipEstimate() argument
12821 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op); in getRecipEstimate()
19444 TargetLowering::DAGCombinerInfo &DCI, in PerformShuffleCombine256() argument
19513 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
19524 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
19531 return DCI.CombineTo(N, InsV); in PerformShuffleCombine256()
19548 TargetLowering::DAGCombinerInfo &DCI, in combineX86ShuffleChain() argument
19564 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input), in combineX86ShuffleChain()
19601 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19606 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19607 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op), in combineX86ShuffleChain()
19619 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19621 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19622 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op), in combineX86ShuffleChain()
19633 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19635 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19636 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op), in combineX86ShuffleChain()
19667 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19669 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19670 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op), in combineX86ShuffleChain()
19700 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19703 DCI.AddToWorklist(PSHUFBMaskOp.getNode()); in combineX86ShuffleChain()
19705 DCI.AddToWorklist(Op.getNode()); in combineX86ShuffleChain()
19706 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op), in combineX86ShuffleChain()
19748 TargetLowering::DAGCombinerInfo &DCI, in combineX86ShufflesRecursively() argument
19829 HasPSHUFB, DAG, DCI, Subtarget)) in combineX86ShufflesRecursively()
19839 HasPSHUFB, DAG, DCI, Subtarget)) in combineX86ShufflesRecursively()
19855 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI, in combineX86ShufflesRecursively()
19908 TargetLowering::DAGCombinerInfo &DCI) { in combineRedundantDWordShuffle() argument
20041 TargetLowering::DAGCombinerInfo &DCI) { in combineRedundantHalfShuffle() argument
20078 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true); in combineRedundantHalfShuffle()
20096 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true); in combineRedundantHalfShuffle()
20103 TargetLowering::DAGCombinerInfo &DCI, in PerformTargetShuffleCombine() argument
20122 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true); in PerformTargetShuffleCombine()
20133 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI)) in PerformTargetShuffleCombine()
20146 DCI.AddToWorklist(V.getNode()); in PerformTargetShuffleCombine()
20149 DCI.AddToWorklist(V.getNode()); in PerformTargetShuffleCombine()
20182 DCI.AddToWorklist(V.getNode()); in PerformTargetShuffleCombine()
20193 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI)) in PerformTargetShuffleCombine()
20259 TargetLowering::DAGCombinerInfo &DCI, in PerformShuffleCombine() argument
20268 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) in PerformShuffleCombine()
20280 return PerformShuffleCombine256(N, DAG, DCI, Subtarget); in PerformShuffleCombine()
20294 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() && in PerformShuffleCombine()
20346 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget); in PerformShuffleCombine()
20359 DCI, Subtarget)) in PerformShuffleCombine()
20370 TargetLowering::DAGCombinerInfo &DCI, in PerformTruncateCombine() argument
20380 TargetLowering::DAGCombinerInfo &DCI) { in XFormVExtractWithShuffleIntoLoad() argument
20381 if (DCI.isBeforeLegalizeOps()) in XFormVExtractWithShuffleIntoLoad()
20496 TargetLowering::DAGCombinerInfo &DCI) { in PerformEXTRACT_VECTOR_ELTCombine() argument
20497 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI); in PerformEXTRACT_VECTOR_ELTCombine()
20766 TargetLowering::DAGCombinerInfo &DCI, in PerformSELECTCombine() argument
20935 DCI.AddToWorklist(Cond.getNode()); in PerformSELECTCombine()
21213 !DCI.isBeforeLegalize()) { in PerformSELECTCombine()
21223 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() && in PerformSELECTCombine()
21224 !DCI.isBeforeLegalize() && in PerformSELECTCombine()
21261 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(), in PerformSELECTCombine()
21262 DCI.isBeforeLegalizeOps()); in PerformSELECTCombine()
21291 DCI.CommitTargetLoweringOpt(TLO); in PerformSELECTCombine()
21485 TargetLowering::DAGCombinerInfo &DCI, in PerformCMOVCombine() argument
21547 return DCI.CombineTo(N, Cond, SDValue()); in PerformCMOVCombine()
21564 return DCI.CombineTo(N, Cond, SDValue()); in PerformCMOVCombine()
21607 return DCI.CombineTo(N, Cond, SDValue()); in PerformCMOVCombine()
21628 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in PerformCMOVCombine()
21791 TargetLowering::DAGCombinerInfo &DCI) { in PerformMulCombine() argument
21792 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) in PerformMulCombine()
21845 DCI.CombineTo(N, NewMul, false); in PerformMulCombine()
21924 TargetLowering::DAGCombinerInfo &DCI, in PerformShiftCombine() argument
21944 TargetLowering::DAGCombinerInfo &DCI, in CMPEQCombine() argument
22076 TargetLowering::DAGCombinerInfo &DCI, in WidenMaskArithmetic() argument
22155 TargetLowering::DAGCombinerInfo &DCI, in VectorZextCombine() argument
22245 TargetLowering::DAGCombinerInfo &DCI, in PerformAndCombine() argument
22247 if (DCI.isBeforeLegalizeOps()) in PerformAndCombine()
22250 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget)) in PerformAndCombine()
22253 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget)) in PerformAndCombine()
22307 TargetLowering::DAGCombinerInfo &DCI, in PerformOrCombine() argument
22309 if (DCI.isBeforeLegalizeOps()) in PerformOrCombine()
22312 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); in PerformOrCombine()
22503 TargetLowering::DAGCombinerInfo &DCI, in PerformXorCombine() argument
22505 if (DCI.isBeforeLegalizeOps()) in PerformXorCombine()
22519 TargetLowering::DAGCombinerInfo &DCI, in PerformLOADCombine() argument
22533 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) { in PerformLOADCombine()
22559 return DCI.CombineTo(N, NewVec, TF, true); in PerformLOADCombine()
22567 TargetLowering::DAGCombinerInfo &DCI, in PerformMLOADCombine() argument
22643 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true); in PerformMLOADCombine()
23175 TargetLowering::DAGCombinerInfo &DCI) { in PerformBTCombine() argument
23182 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformBTCombine()
23183 !DCI.isBeforeLegalizeOps()); in PerformBTCombine()
23187 DCI.CommitTargetLoweringOpt(TLO); in PerformBTCombine()
23241 TargetLowering::DAGCombinerInfo &DCI, in PerformSExtCombine() argument
23260 if (!DCI.isBeforeLegalizeOps()) in PerformSExtCombine()
23267 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget); in PerformSExtCombine()
23316 TargetLowering::DAGCombinerInfo &DCI, in PerformZExtCombine() argument
23353 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget); in PerformZExtCombine()
23527 TargetLowering::DAGCombinerInfo &DCI, in PerformSETCCCombine() argument
23571 TargetLowering::DAGCombinerInfo &DCI, in PerformBrCondCombine() argument
23681 X86TargetLowering::DAGCombinerInfo &DCI) { in PerformADCCombine() argument
23698 return DCI.CombineTo(N, Res1, CarryOut); in PerformADCCombine()
23795 TargetLowering::DAGCombinerInfo &DCI, in performVZEXTCombine() argument
23860 DAGCombinerInfo &DCI) const { in PerformDAGCombine()
23861 SelectionDAG &DAG = DCI.DAG; in PerformDAGCombine()
23865 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI); in PerformDAGCombine()
23869 return PerformSELECTCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23871 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23874 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); in PerformDAGCombine()
23875 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); in PerformDAGCombine()
23878 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23879 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23880 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23881 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23882 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23883 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23895 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); in PerformDAGCombine()
23898 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23899 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23902 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget); in PerformDAGCombine()
23904 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23905 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23906 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
23921 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); in PerformDAGCombine()