684     setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);  in X86TargetLowering()
775   setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v1i64, Expand);  in X86TargetLowering()
836     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);  in X86TargetLowering()
837     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);  in X86TargetLowering()
838     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);  in X86TargetLowering()
885     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2f64, Custom);  in X86TargetLowering()
889       setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Custom);  in X86TargetLowering()
983     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i8, Custom);  in X86TargetLowering()
984     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i16, Custom);  in X86TargetLowering()
985     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4i32, Custom);  in X86TargetLowering()
986     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v4f32, Custom);  in X86TargetLowering()
996       setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v2i64, Custom);  in X86TargetLowering()
1210       setOperationAction(ISD::INSERT_VECTOR_ELT,  VT, Custom);  in X86TargetLowering()
1345     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v16i1, Custom);  in X86TargetLowering()
1346     setOperationAction(ISD::INSERT_VECTOR_ELT,  MVT::v8i1, Custom);  in X86TargetLowering()
1399         setOperationAction(ISD::INSERT_VECTOR_ELT,   VT, Custom);  in X86TargetLowering()
4482         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,  in LowerBuildVectorv16i8()
4519         V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,  in LowerBuildVectorv16i8()
4550       V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,  in LowerBuildVectorv8i16()
5065   if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))  in buildFromShuffleMostly()
5125     NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),  in buildFromShuffleMostly()
5192     return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,  in LowerBUILD_VECTORvXi1()
5712           return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,  in LowerBUILD_VECTOR()
5906         Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,  in LowerBUILD_VECTOR()
10580     SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,  in InsertBitToMaskVector()
10641     V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,  in LowerINSERT_VECTOR_ELT()
13903       Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,  in LowerExtendedLoad()
16241         } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {  in LowerScalarVariableShift()
17194   case ISD::INSERT_VECTOR_ELT:  return LowerINSERT_VECTOR_ELT(Op, DAG);  in LowerOperation()