Lines Matching refs:R2

14 …ips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-BE
15 …mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A
16 …sel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-LE
17 …mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A
33 ; 32R2-NO-FP64A-LE-NOT:     addiu   $sp, $sp
34 ; 32R2-NO-FP64A-LE:         mtc1    $4, $f0
35 ; 32R2-NO-FP64A-LE:         mthc1   $5, $f0
37 ; 32R2-NO-FP64A-BE-NOT:     addiu   $sp, $sp
38 ; 32R2-NO-FP64A-BE:         mtc1    $5, $f0
39 ; 32R2-NO-FP64A-BE:         mthc1   $4, $f0
41 ; 32R2-FP64A:               addiu   $sp, $sp, -8
42 ; 32R2-FP64A:               sw      $4, 0($sp)
43 ; 32R2-FP64A:               sw      $5, 4($sp)
44 ; 32R2-FP64A:               ldc1    $f0, 0($sp)
55 ; 32R2-NO-FP64A-LE:     mtc1    $6, $f0
56 ; 32R2-NO-FP64A-LE:     mthc1   $7, $f0
58 ; 32R2-NO-FP64A-BE:     mtc1    $7, $f0
59 ; 32R2-NO-FP64A-BE:     mthc1   $6, $f0
61 ; 32R2-FP64A:           addiu   $sp, $sp, -8
62 ; 32R2-FP64A:           sw      $6, 0($sp)
63 ; 32R2-FP64A:           sw      $7, 4($sp)
64 ; 32R2-FP64A:           ldc1    $f0, 0($sp)
75 ; 32R2-NO-FP64A-LE:     mtc1    $6, $f0
76 ; 32R2-NO-FP64A-LE:     mthc1   $7, $f0
78 ; 32R2-NO-FP64A-BE:     mtc1    $7, $f0
79 ; 32R2-NO-FP64A-BE:     mthc1   $6, $f0
81 ; 32R2-FP64A:           addiu   $sp, $sp, -8
82 ; 32R2-FP64A:           sw      $6, 0($sp)
83 ; 32R2-FP64A:           sw      $7, 4($sp)
84 ; 32R2-FP64A:           ldc1    $f0, 0($sp)
95 ; 32R2-NO-FP64A-LE:     mtc1    $6, $f0
96 ; 32R2-NO-FP64A-LE:     mthc1   $7, $f0
98 ; 32R2-NO-FP64A-BE:     mtc1    $7, $f0
99 ; 32R2-NO-FP64A-BE:     mthc1   $6, $f0
101 ; 32R2-FP64A:           addiu   $sp, $sp, -8
102 ; 32R2-FP64A:           sw      $6, 0($sp)
103 ; 32R2-FP64A:           sw      $7, 4($sp)
104 ; 32R2-FP64A:           ldc1    $f0, 0($sp)
116 ; 32R2-NO-FP64A-LE-DAG:     mtc1    $4, $[[T0:f[0-9]+]]
117 ; 32R2-NO-FP64A-LE-DAG:     mthc1   $5, $[[T0:f[0-9]+]]
118 ; 32R2-NO-FP64A-LE-DAG:     mtc1    $6, $[[T1:f[0-9]+]]
119 ; 32R2-NO-FP64A-LE-DAG:     mthc1   $7, $[[T1:f[0-9]+]]
120 ; 32R2-NO-FP64A-LE:         sub.d   $f0, $[[T0]], $[[T1]]
122 ; 32R2-NO-FP64A-BE-DAG:     mtc1    $5, $[[T0:f[0-9]+]]
123 ; 32R2-NO-FP64A-BE-DAG:     mthc1   $4, $[[T0:f[0-9]+]]
124 ; 32R2-NO-FP64A-BE-DAG:     mtc1    $7, $[[T1:f[0-9]+]]
125 ; 32R2-NO-FP64A-BE-DAG:     mthc1   $6, $[[T1:f[0-9]+]]
126 ; 32R2-NO-FP64A-BE:         sub.d   $f0, $[[T0]], $[[T1]]
128 ; 32R2-FP64A:               addiu   $sp, $sp, -8
129 ; 32R2-FP64A:               sw      $6, 0($sp)
130 ; 32R2-FP64A:               sw      $7, 4($sp)
131 ; 32R2-FP64A:               ldc1    $[[T1:f[0-9]+]], 0($sp)
132 ; 32R2-FP64A:               sw      $4, 0($sp)
133 ; 32R2-FP64A:               sw      $5, 4($sp)
134 ; 32R2-FP64A:               ldc1    $[[T0:f[0-9]+]], 0($sp)
135 ; 32R2-FP64A:               sub.d   $f0, $[[T0]], $[[T1]]
147 ; 32R2-NO-FP64A-LE-DAG: mfc1    $6, $f0
148 ; 32R2-NO-FP64A-LE-DAG: mfhc1   $7, $f0
150 ; 32R2-NO-FP64A-BE-DAG: mfc1    $7, $f0
151 ; 32R2-NO-FP64A-BE-DAG: mfhc1   $6, $f0
153 ; 32R2-FP64A:           addiu   $sp, $sp, -32
154 ; 32R2-FP64A:           sdc1    $f0, 16($sp)
155 ; 32R2-FP64A:           lw      $6, 16($sp)
157 ; 32R2-FP64A:           sdc1    $f0, 16($sp)
158 ; 32R2-FP64A:           lw      $7, 20($sp)