Lines Matching refs:shl
7 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
8 ret <8 x i16> %shl
17 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
18 ret <8 x i16> %shl
27 %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
28 ret <8 x i16> %shl
37 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
38 ret <4 x i32> %shl
47 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
48 ret <4 x i32> %shl
57 %shl = shl <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
58 ret <4 x i32> %shl
67 %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
68 ret <2 x i64> %shl
77 %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
78 ret <2 x i64> %shl
87 %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
88 ret <2 x i64> %shl
99 %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
100 ret <8 x i16> %shl
109 %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
110 ret <8 x i16> %shl
119 %shl = ashr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
120 ret <8 x i16> %shl
129 %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
130 ret <4 x i32> %shl
139 %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
140 ret <4 x i32> %shl
149 %shl = ashr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
150 ret <4 x i32> %shl
161 %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
162 ret <8 x i16> %shl
171 %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
172 ret <8 x i16> %shl
181 %shl = lshr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
182 ret <8 x i16> %shl
191 %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
192 ret <4 x i32> %shl
201 %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
202 ret <4 x i32> %shl
211 %shl = lshr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
212 ret <4 x i32> %shl
221 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
222 ret <2 x i64> %shl
231 %shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
232 ret <2 x i64> %shl
241 %shl = lshr <2 x i64> %InVec, <i64 63, i64 63>
242 ret <2 x i64> %shl
272 %srl0 = shl <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
290 %shl0 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
291 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
300 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4>
310 %shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5>
320 %shl = shl <4 x i32> %zext, <i32 2, i32 2, i32 2, i32 2>
321 ret <4 x i32> %shl
339 %shl0 = shl <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2>
341 %shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17>
365 %sra = shl <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3>