Lines Matching refs:prog
39 struct nv50_program *prog = (struct nv50_program *)info->driverPriv; in nv50_vertprog_assign_slots() local
44 prog->in[i].id = i; in nv50_vertprog_assign_slots()
45 prog->in[i].sn = info->in[i].sn; in nv50_vertprog_assign_slots()
46 prog->in[i].si = info->in[i].si; in nv50_vertprog_assign_slots()
47 prog->in[i].hw = n; in nv50_vertprog_assign_slots()
48 prog->in[i].mask = info->in[i].mask; in nv50_vertprog_assign_slots()
50 prog->vp.attrs[(4 * i) / 32] |= info->in[i].mask << ((4 * i) % 32); in nv50_vertprog_assign_slots()
56 prog->in_nr = info->numInputs; in nv50_vertprog_assign_slots()
61 prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_INSTANCE_ID; in nv50_vertprog_assign_slots()
64 prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_VERTEX_ID; in nv50_vertprog_assign_slots()
65 prog->vp.attrs[2] |= NV50_3D_VP_GP_BUILTIN_ATTR_EN_UNK12; in nv50_vertprog_assign_slots()
77 if (prog->vp.attrs[0] == 0 && in nv50_vertprog_assign_slots()
78 prog->vp.attrs[1] == 0 && in nv50_vertprog_assign_slots()
79 prog->vp.attrs[2] == 0) in nv50_vertprog_assign_slots()
80 prog->vp.attrs[0] |= 0xf; in nv50_vertprog_assign_slots()
92 prog->vp.psiz = i; in nv50_vertprog_assign_slots()
95 prog->vp.clpd[info->out[i].si] = n; in nv50_vertprog_assign_slots()
98 prog->vp.edgeflag = i; in nv50_vertprog_assign_slots()
101 prog->vp.bfc[info->out[i].si] = i; in nv50_vertprog_assign_slots()
106 prog->out[i].id = i; in nv50_vertprog_assign_slots()
107 prog->out[i].sn = info->out[i].sn; in nv50_vertprog_assign_slots()
108 prog->out[i].si = info->out[i].si; in nv50_vertprog_assign_slots()
109 prog->out[i].hw = n; in nv50_vertprog_assign_slots()
110 prog->out[i].mask = info->out[i].mask; in nv50_vertprog_assign_slots()
116 prog->out_nr = info->numOutputs; in nv50_vertprog_assign_slots()
117 prog->max_out = n; in nv50_vertprog_assign_slots()
119 if (prog->vp.psiz < info->numOutputs) in nv50_vertprog_assign_slots()
120 prog->vp.psiz = prog->out[prog->vp.psiz].hw; in nv50_vertprog_assign_slots()
128 struct nv50_program *prog = (struct nv50_program *)info->driverPriv; in nv50_fragprog_assign_slots() local
152 prog->fp.interp |= info->in[i].mask << 24; in nv50_fragprog_assign_slots()
163 prog->vp.bfc[info->in[i].si] = j; in nv50_fragprog_assign_slots()
165 prog->in[j].id = i; in nv50_fragprog_assign_slots()
166 prog->in[j].mask = info->in[i].mask; in nv50_fragprog_assign_slots()
167 prog->in[j].sn = info->in[i].sn; in nv50_fragprog_assign_slots()
168 prog->in[j].si = info->in[i].si; in nv50_fragprog_assign_slots()
169 prog->in[j].linear = info->in[i].linear; in nv50_fragprog_assign_slots()
171 prog->in_nr++; in nv50_fragprog_assign_slots()
174 if (!(prog->fp.interp & (8 << 24))) { in nv50_fragprog_assign_slots()
176 prog->fp.interp |= 8 << 24; in nv50_fragprog_assign_slots()
179 for (i = 0; i < prog->in_nr; ++i) { in nv50_fragprog_assign_slots()
180 int j = prog->in[i].id; in nv50_fragprog_assign_slots()
182 prog->in[i].hw = nintp; in nv50_fragprog_assign_slots()
184 if (prog->in[i].mask & (1 << c)) in nv50_fragprog_assign_slots()
188 nflat = (n < m) ? (nintp - prog->in[n].hw) : 0; in nv50_fragprog_assign_slots()
189 nintp -= bitcount4(prog->fp.interp >> 24); /* subtract position inputs */ in nv50_fragprog_assign_slots()
192 prog->fp.interp |= nvary << NV50_3D_FP_INTERPOLANT_CTRL_COUNT_NONFLAT__SHIFT; in nv50_fragprog_assign_slots()
193 prog->fp.interp |= nintp << NV50_3D_FP_INTERPOLANT_CTRL_COUNT__SHIFT; in nv50_fragprog_assign_slots()
196 prog->fp.colors = 4 << NV50_3D_SEMANTIC_COLOR_FFC0_ID__SHIFT; in nv50_fragprog_assign_slots()
198 if (prog->vp.bfc[i] < 0xff) in nv50_fragprog_assign_slots()
199 prog->fp.colors += bitcount4(prog->in[prog->vp.bfc[i]].mask) << 16; in nv50_fragprog_assign_slots()
204 prog->fp.flags[0] |= NV50_3D_FP_CONTROL_MULTIPLE_RESULTS; in nv50_fragprog_assign_slots()
207 prog->out[i].id = i; in nv50_fragprog_assign_slots()
208 prog->out[i].sn = info->out[i].sn; in nv50_fragprog_assign_slots()
209 prog->out[i].si = info->out[i].si; in nv50_fragprog_assign_slots()
210 prog->out[i].mask = info->out[i].mask; in nv50_fragprog_assign_slots()
214 prog->out[i].hw = info->out[i].si * 4; in nv50_fragprog_assign_slots()
217 info->out[i].slot[c] = prog->out[i].hw + c; in nv50_fragprog_assign_slots()
219 prog->max_out = MAX2(prog->max_out, prog->out[i].hw + 4); in nv50_fragprog_assign_slots()
223 info->out[info->io.sampleMask].slot[0] = prog->max_out++; in nv50_fragprog_assign_slots()
226 info->out[info->io.fragDepth].slot[2] = prog->max_out++; in nv50_fragprog_assign_slots()
228 if (!prog->max_out) in nv50_fragprog_assign_slots()
229 prog->max_out = 4; in nv50_fragprog_assign_slots()
303 nv50_program_translate(struct nv50_program *prog, uint16_t chipset) in nv50_program_translate() argument
307 const uint8_t map_undef = (prog->type == PIPE_SHADER_VERTEX) ? 0x40 : 0x80; in nv50_program_translate()
313 info->type = prog->type; in nv50_program_translate()
316 info->bin.source = (void *)prog->pipe.tokens; in nv50_program_translate()
320 info->io.genUserClip = prog->vp.clpd_nr; in nv50_program_translate()
324 prog->vp.bfc[0] = 0xff; in nv50_program_translate()
325 prog->vp.bfc[1] = 0xff; in nv50_program_translate()
326 prog->vp.edgeflag = 0xff; in nv50_program_translate()
327 prog->vp.clpd[0] = map_undef; in nv50_program_translate()
328 prog->vp.clpd[1] = map_undef; in nv50_program_translate()
329 prog->vp.psiz = map_undef; in nv50_program_translate()
330 prog->gp.primid = 0x80; in nv50_program_translate()
332 info->driverPriv = prog; in nv50_program_translate()
349 prog->code = info->bin.code; in nv50_program_translate()
350 prog->code_size = info->bin.codeSize; in nv50_program_translate()
351 prog->fixups = info->bin.relocData; in nv50_program_translate()
352 prog->max_gpr = MAX2(4, (info->bin.maxGPR >> 1) + 1); in nv50_program_translate()
353 prog->tls_space = info->bin.tlsSpace; in nv50_program_translate()
355 if (prog->type == PIPE_SHADER_FRAGMENT) { in nv50_program_translate()
357 prog->fp.flags[0] |= NV50_3D_FP_CONTROL_EXPORTS_Z; in nv50_program_translate()
358 prog->fp.flags[1] = 0x11; in nv50_program_translate()
361 prog->fp.flags[0] |= NV50_3D_FP_CONTROL_USES_KIL; in nv50_program_translate()
364 if (prog->pipe.stream_output.num_outputs) in nv50_program_translate()
365 prog->so = nv50_program_create_strmout_state(info, in nv50_program_translate()
366 &prog->pipe.stream_output); in nv50_program_translate()
374 nv50_program_upload_code(struct nv50_context *nv50, struct nv50_program *prog) in nv50_program_upload_code() argument
378 uint32_t size = align(prog->code_size, 0x40); in nv50_program_upload_code()
380 switch (prog->type) { in nv50_program_upload_code()
389 ret = nouveau_heap_alloc(heap, size, prog, &prog->mem); in nv50_program_upload_code()
401 prog->code_base = prog->mem->start; in nv50_program_upload_code()
403 ret = nv50_tls_realloc(nv50->screen, prog->tls_space); in nv50_program_upload_code()
409 if (prog->fixups) in nv50_program_upload_code()
410 nv50_ir_relocate_code(prog->fixups, prog->code, prog->code_base, 0, 0); in nv50_program_upload_code()
413 (prog->type << NV50_CODE_BO_SIZE_LOG2) + prog->code_base, in nv50_program_upload_code()
414 NOUVEAU_BO_VRAM, prog->code_size, prog->code); in nv50_program_upload_code()