34 void r300_parse_chipset(uint32_t pci_id, struct r300_capabilities* caps)  in r300_parse_chipset()  argument
39             caps->family = CHIP_FAMILY_##chipfamily; \  in r300_parse_chipset()
51     caps->high_second_pipe = FALSE;  in r300_parse_chipset()
52     caps->num_vert_fpus = 0;  in r300_parse_chipset()
53     caps->hiz_ram = 0;  in r300_parse_chipset()
54     caps->zmask_ram = 0;  in r300_parse_chipset()
57     switch (caps->family) {  in r300_parse_chipset()
60         caps->high_second_pipe = TRUE;  in r300_parse_chipset()
61         caps->num_vert_fpus = 4;  in r300_parse_chipset()
62         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
63         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
68         caps->high_second_pipe = TRUE;  in r300_parse_chipset()
69         caps->num_vert_fpus = 2;  in r300_parse_chipset()
70         caps->zmask_ram = RV3xx_ZMASK_SIZE;  in r300_parse_chipset()
74         caps->high_second_pipe = TRUE;  in r300_parse_chipset()
75         caps->num_vert_fpus = 2;  in r300_parse_chipset()
76         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
77         caps->zmask_ram = RV3xx_ZMASK_SIZE;  in r300_parse_chipset()
88         caps->zmask_ram = RV3xx_ZMASK_SIZE;  in r300_parse_chipset()
97         caps->num_vert_fpus = 6;  in r300_parse_chipset()
98         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
99         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
103         caps->num_vert_fpus = 8;  in r300_parse_chipset()
104         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
105         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
109         caps->num_vert_fpus = 2;  in r300_parse_chipset()
110         caps->hiz_ram = R300_HIZ_LIMIT;  in r300_parse_chipset()
111         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
115         caps->num_vert_fpus = 5;  in r300_parse_chipset()
116         caps->hiz_ram = RV530_HIZ_LIMIT;  in r300_parse_chipset()
117         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
123         caps->num_vert_fpus = 8;  in r300_parse_chipset()
124         caps->hiz_ram = RV530_HIZ_LIMIT;  in r300_parse_chipset()
125         caps->zmask_ram = PIPE_ZMASK_SIZE;  in r300_parse_chipset()
129     caps->num_tex_units = 16;  in r300_parse_chipset()
130     caps->is_r400 = caps->family >= CHIP_FAMILY_R420 && caps->family < CHIP_FAMILY_RV515;  in r300_parse_chipset()
131     caps->is_r500 = caps->family >= CHIP_FAMILY_RV515;  in r300_parse_chipset()
132     caps->is_rv350 = caps->family >= CHIP_FAMILY_RV350;  in r300_parse_chipset()
133     caps->z_compress = caps->is_rv350 ? R300_ZCOMP_8X8 : R300_ZCOMP_4X4;  in r300_parse_chipset()
134     caps->dxtc_swizzle = caps->is_r400 || caps->is_r500;  in r300_parse_chipset()
135     caps->has_us_format = caps->family == CHIP_FAMILY_R520;  in r300_parse_chipset()
136     caps->has_tcl = caps->num_vert_fpus > 0;  in r300_parse_chipset()
138     if (caps->has_tcl) {  in r300_parse_chipset()
139         caps->has_tcl = debug_get_bool_option("RADEON_NO_TCL", FALSE) ? FALSE : TRUE;  in r300_parse_chipset()