Lines Matching refs:m32

33 adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
34 adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000]
37 adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
38 adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
39 adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
40 adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
71 addl imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
73 addl r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
74 addl m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
98 andl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
100 andl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
101 andl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430]
115 bsfl m32.ud[0x75318642] r32.ud[0] => 1.ud[1]
121 bsrl m32.ud[0x75318642] r32.ud[0] => 1.ud[30]
136 btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
137 btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
140 btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
141 btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
160 btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
161 btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
164 btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
165 btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
184 btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
185 btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
188 btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
189 btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
208 btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
209 btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
212 btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
213 btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
384 cmpl imm8[3] m32.ud[2] => eflags[0x010,0x010]
385 cmpl imm8[2] m32.ud[3] => eflags[0x010,0x000]
386 cmpl imm8[12] m32.ud[12] => eflags[0x044,0x044]
387 cmpl imm8[12] m32.ud[34] => eflags[0x044,0x000]
388 cmpl imm8[34] m32.ud[12] => eflags[0x081,0x081]
389 cmpl imm8[12] m32.ud[34] => eflags[0x081,0x000]
390 cmpl imm8[100] m32.sd[-2147483600] => eflags[0x800,0x800]
391 cmpl imm8[50] m32.sd[-50] => eflags[0x800,0x000]
392 cmpl imm8[-50] m32.sd[50] => eflags[0x800,0x000]
393 cmpl imm8[-100] m32.sd[2147483600] => eflags[0x800,0x800]
414 cmpl imm32[3] m32.ud[2] => eflags[0x010,0x010]
415 cmpl imm32[2] m32.ud[3] => eflags[0x010,0x000]
416 cmpl imm32[12] m32.ud[12] => eflags[0x044,0x044]
417 cmpl imm32[12] m32.ud[34] => eflags[0x044,0x000]
418 cmpl imm32[34] m32.ud[12] => eflags[0x081,0x081]
419 cmpl imm32[12] m32.ud[34] => eflags[0x081,0x000]
420 cmpl imm32[100] m32.sd[-2147483600] => eflags[0x800,0x800]
421 cmpl imm32[50] m32.sd[-50] => eflags[0x800,0x000]
422 cmpl imm32[-50] m32.sd[50] => eflags[0x800,0x000]
423 cmpl imm32[-100] m32.sd[2147483600] => eflags[0x800,0x800]
434 cmpl r32.ud[3] m32.ud[2] => eflags[0x010,0x010]
435 cmpl r32.ud[2] m32.ud[3] => eflags[0x010,0x000]
436 cmpl r32.ud[12] m32.ud[12] => eflags[0x044,0x044]
437 cmpl r32.ud[12] m32.ud[34] => eflags[0x044,0x000]
438 cmpl r32.ud[34] m32.ud[12] => eflags[0x081,0x081]
439 cmpl r32.ud[12] m32.ud[34] => eflags[0x081,0x000]
440 cmpl r32.ud[100] m32.sd[-2147483600] => eflags[0x800,0x800]
441 cmpl r32.ud[50] m32.sd[-50] => eflags[0x800,0x000]
442 cmpl r32.sd[-50] m32.sd[50] => eflags[0x800,0x000]
443 cmpl r32.sd[-100] m32.sd[2147483600] => eflags[0x800,0x800]
444 cmpl m32.ud[3] r32.ud[2] => eflags[0x010,0x010]
445 cmpl m32.ud[2] r32.ud[3] => eflags[0x010,0x000]
446 cmpl m32.ud[12] r32.ud[12] => eflags[0x044,0x044]
447 cmpl m32.ud[12] r32.ud[34] => eflags[0x044,0x000]
448 cmpl m32.ud[34] r32.ud[12] => eflags[0x081,0x081]
449 cmpl m32.ud[12] r32.ud[34] => eflags[0x081,0x000]
450 cmpl m32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
451 cmpl m32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
452 cmpl m32.sd[-50] r32.sd[50] => eflags[0x800,0x000]
453 ###cmpl m32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800]
544 cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => eflags[0x40,0x40] eax.ud[123…
545 cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => eflags[0x40,0x00] eax.ud[345…
561 decl m32.ud[12345678] => 0.ud[12345677]
569 divl edx.ud[251958] eax.ud[673192206] : m32.ud[87654321] => eax.ud[12345678] edx.ud[20783136]
577 idivl edx.sd[251958] eax.sd[673192206] : m32.sd[-87654321] => eax.sd[-12345678] edx.sd[20783136]
585 imull eax.sd[12345678] : m32.sd[-12345678] => edx.sd[-35488] eax.sd[-260846532]
598 imull imm8[123] m32.ud[67890] r32.ud[0] => 2.ud[8350470]
601 imull imm32[12345] m32.ud[67890] r32.ud[0] => 2.ud[838102050]
603 imull m32.ud[12345] r32.ud[67890] => 1.ud[838102050]
617 incl m32.ud[12345678] => 0.ud[12345679]
633 movl imm32[12345678] m32.ud[0] => 1.ud[12345678]
635 movl r32.ud[12345678] m32.ud[0] => 1.ud[12345678]
636 movl m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
668 mull eax.ud[12345678] : m32.ud[12345678] => edx.ud[35487] eax.ud[260846532]
676 negl m32.sd[-12345678] => 0.sd[12345678]
684 notl m32.ud[0xff00f0ca] => 0.ud[0x00ff0f35]
703 orl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
705 orl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
706 orl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779]
730 ###rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
732 ###rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
734 ###rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
754 rcrl eflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
756 rcrl eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
758 rcrl eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
778 roll m32.ud[0xff00f0ca] => 0.ud[0xfe01e195]
780 roll imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
782 roll cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
802 rorl m32.ud[0xff00f0ca] => 0.ud[0x7f807865]
804 rorl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
806 rorl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
828 sall m32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
830 sall imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
832 sall cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
852 sarl m32.ud[0xff00f0ca] => 0.ud[0xff807865]
854 sarl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
856 sarl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
895 sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643]
896 sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642]
899 ###sbbl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
900 ###sbbl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642]
901 sbbl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
902 sbbl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
1122 shll m32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
1124 shll imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
1126 shll cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
1146 shrl m32.ud[0xff00f0ca] => 0.ud[0x7f807865]
1148 shrl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
1150 shrl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
1166 ###shldl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
1168 ###shldl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
1170 shldl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
1172 shldl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
1190 shrdl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865]
1192 shrdl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
1194 shrdl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865]
1196 shrdl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
1227 subl r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
1228 subl m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
1296 testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1297 testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1298 testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1299 testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1300 testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1306 testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
1307 testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
1308 testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
1309 testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
1310 testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
1341 xaddl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[99999999]
1355 xchgl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
1356 xchgl m32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
1378 xorl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
1380 xorl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
1381 xorl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349]