| /external/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
223 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate()
460 unsigned PredReg; in rewriteT2FrameIndex() local
630 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getITInstrPredicate()
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| D | ARMLoadStoreOptimizer.cpp | 382 ARMCC::CondCodes Pred, unsigned PredReg) { in UpdateBaseRegUses()
482 unsigned PredReg, unsigned Scratch, DebugLoc dl, in MergeOps()
734 ARMCC::CondCodes Pred, unsigned PredReg, in MergeOpsUpdate()
833 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR()
910 ARMCC::CondCodes Pred, unsigned PredReg) { in isMatchingDecrement()
945 ARMCC::CondCodes Pred, unsigned PredReg) { in isMatchingIncrement()
1111 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local
1268 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local
1456 ARMCC::CondCodes Pred, unsigned PredReg, in InsertLDR_STR()
1506 unsigned PredReg = 0; in FixInvalidRegPairOp() local
[all …]
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| D | ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool()
86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool()
106 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
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| D | Thumb2SizeReduction.cpp | 581 unsigned PredReg = 0; in ReduceSpecial() local
685 unsigned PredReg = 0; in ReduceTo2Addr() local
782 unsigned PredReg = 0; in ReduceToNarrow() local
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| D | Thumb2ITBlockPass.cpp | 171 unsigned PredReg = 0; in InsertITInstructions() local
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| D | ARMFrameLowering.cpp | 120 unsigned PredReg = 0) { in emitRegPlusImmediate()
134 unsigned PredReg = 0) { in emitSPUpdate()
1792 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
1797 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
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| D | ARMBaseRegisterInfo.cpp | 396 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
747 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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| D | MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
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| D | ARMISelDAGToDAG.cpp | 2488 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2755 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2775 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2794 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
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| D | ARMConstantIslandPass.cpp | 1358 unsigned PredReg = 0; in createNewWater() local
1809 unsigned PredReg = 0; in optimizeThumb2Branches() local
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| D | ARMExpandPseudoInsts.cpp | 656 unsigned PredReg = 0; in ExpandMOV32BitImm() local
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| D | ARMBaseInstrInfo.cpp | 1733 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate()
1763 unsigned PredReg = 0; in commuteInstruction() local
1948 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 495 unsigned PredReg = Cond[Cond.size()-1].getReg(); in getLoopTripCount() local
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