Home
last modified time | relevance | path

Searched defs:RC (Results 1 – 25 of 148) sorted by relevance

123456

/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
/external/llvm/include/llvm/IR/
DIRBuilder.h697 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
711 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
719 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
733 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
741 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
755 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
763 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
775 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
787 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
794 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
[all …]
/external/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot() local
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot() local
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot() local
/external/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp77 const TargetRegisterClass *RC = in getGlobalBaseReg() local
98 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; in getMips16SPAliasReg() local
104 const TargetRegisterClass *RC = in createEhDataRegsFI() local
137 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
DMipsSEFrameLowering.cpp155 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
170 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
213 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
245 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
294 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
348 const TargetRegisterClass *RC = in expandExtractElementF64() local
476 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitPrologue() local
542 const TargetRegisterClass *RC = STI.isABI_N64() ? in emitEpilogue() local
590 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
[all …]
DMipsInstrInfo.h93 const TargetRegisterClass *RC, in storeRegToStackSlot()
101 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp433 const TargetRegisterClass *RC, in PPCEmitLoad()
576 const TargetRegisterClass *RC = in SelectLoad() local
592 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
952 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1015 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1059 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1149 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1311 const TargetRegisterClass *RC = in processCallArgs() local
1323 const TargetRegisterClass *RC = in processCallArgs() local
1640 const TargetRegisterClass *RC = in SelectRet() local
[all …]
/external/llvm/lib/Target/R600/
DSIFixSGPRCopies.cpp140 const TargetRegisterClass *RC in inferRegClassFromUses() local
166 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); in inferRegClassFromDef() local
230 const TargetRegisterClass *RC in runOnMachineFunction() local
236 const TargetRegisterClass *RC = inferRegClassFromUses(TRI, MRI, Reg, in runOnMachineFunction() local
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h127 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
133 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
140 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
146 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
473 const TargetRegisterClass *RC) const { in getMatchingSuperReg()
499 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg()
623 getCrossCopyRegClass(const TargetRegisterClass *RC) const { in getCrossCopyRegClass()
632 getLargestLegalSuperClass(const TargetRegisterClass *RC, in getLargestLegalSuperClass()
645 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
821 const TargetRegisterClass *RC, in saveScavengerRegister()
/external/llvm/lib/CodeGen/
DLiveStackAnalysis.cpp60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
84 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
DTargetRegisterInfo.cpp119 const TargetRegisterClass* RC = *I; in getMinimalPhysRegClass() local
132 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
236 const TargetRegisterClass *RC = in getCommonSuperRegClass() local
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp116 for (const auto &RC : RegisterClasses) in runEnums() local
182 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
957 for (const auto &RC : RegisterClasses) { in runMCDesc() local
997 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1105 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1142 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1151 for (const auto &RC : RegisterClasses) in runTargetDesc() local
1205 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1232 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1247 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
[all …]
DCodeGenRegisters.cpp856 CodeGenRegisterClass &RC = *I; in computeSubClasses() local
878 for (auto &RC : RegClasses) { in computeSubClasses() local
894 for (auto &RC : RegClasses) in computeSubClasses() local
996 for (auto *RC : RCs) { in CodeGenRegBank() local
1007 for (auto &RC : RegClasses) in CodeGenRegBank() local
1037 void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) { in addToMaps()
1049 CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC, in getOrCreateSubClass()
1065 if (CodeGenRegisterClass *RC = Def2RC[Def]) in getRegClass() local
1599 for (auto &RC : RegClasses) { in computeRegUnitSets() local
1704 for (auto &RC : RegClasses) { in computeRegUnitSets() local
[all …]
DCodeGenTarget.cpp235 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs() local
250 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes() local
423 std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC, in LoadIntrinsics()
/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.cpp29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp73 const TargetRegisterClass *RC, in storeRegToStackSlot()
101 const TargetRegisterClass *RC, in loadRegFromStackSlot()
DARMFastISel.cpp287 const TargetRegisterClass *RC, in fastEmitInst_r()
309 const TargetRegisterClass *RC, in fastEmitInst_rr()
337 const TargetRegisterClass *RC, in fastEmitInst_rrr()
369 const TargetRegisterClass *RC, in fastEmitInst_ri()
395 const TargetRegisterClass *RC, in fastEmitInst_rri()
425 const TargetRegisterClass *RC, in fastEmitInst_i()
521 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
537 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
587 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass in ARMMaterializeGV() local
720 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca() local
[all …]
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp48 const TargetRegisterClass *RC, in storeRegToStackSlot()
66 const TargetRegisterClass *RC, in loadRegFromStackSlot()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp334 const TargetRegisterClass *RC = nullptr; in X86FastEmitLoad() local
584 const TargetRegisterClass *RC = nullptr; in handleConstantAddresses() local
1506 const TargetRegisterClass *RC = nullptr; in X86SelectShift() local
1590 const TargetRegisterClass *RC; in X86SelectDivRem() member
1749 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect() local
1925 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect() local
2013 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect() local
2041 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect() local
2076 const TargetRegisterClass *RC = nullptr; in X86SelectSIToFP() local
2107 const TargetRegisterClass *RC) { in X86SelectFPExtOrFPTrunc()
[all …]
DX86RegisterInfo.cpp100 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg()
125 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, in getLargestLegalSuperClass()
203 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
/external/clang/test/CodeGenCXX/
Ddevirtualize-virtual-function-calls-final.cpp187 struct RC final : public RA { struct
188 virtual C *f() { in f()
194 virtual C *operator-() { in operator -()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1689 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) { in createResultReg()
1711 const TargetRegisterClass *RC) { in fastEmitInst_()
1720 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_r()
1741 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rr()
1765 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rrr()
1793 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_ri()
1815 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rii()
1840 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rf()
1862 const TargetRegisterClass *RC, unsigned Op0, in fastEmitInst_rri()
1888 const TargetRegisterClass *RC, in fastEmitInst_rrii()
[all …]
DResourcePriorityQueue.cpp369 const TargetRegisterClass *RC = *I; in regPressureDelta() local
376 const TargetRegisterClass *RC = *I; in regPressureDelta() local
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
500 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
/external/llvm/lib/Target/R600/MCTargetDesc/
DSIMCCodeEmitter.cpp205 const MCRegisterClass &RC = MRI.getRegClass(RCID); in EncodeInstruction() local
277 const MCRegisterClass &RC = MRI.getRegClass(RCID); in getMachineOpValue() local
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp40 const TargetRegisterClass *RC, in storeRegToStackSlot()
68 const TargetRegisterClass *RC, in loadRegFromStackSlot()

123456