Searched defs:RegClass (Results 1 – 13 of 13) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 45 std::unique_ptr<RCInfo[]> RegClass; variable
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| D | RegisterScavenging.h | 153 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1566 SDValue RegClass = in createGPRPairNode() local
1577 SDValue RegClass = in createSRegPairNode() local
1588 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32); in createDRegPairNode() local
1598 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in createQRegPairNode() local
1609 SDValue RegClass = in createQuadSRegsNode() local
1624 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32); in createQuadDRegsNode() local
1638 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32); in createQuadQRegsNode() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 92 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister()
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| D | TargetInstrInfo.cpp | 49 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelDAGToDAG.cpp | 173 int RegClass = Desc.OpInfo[OpIdx].RegClass; in getOperandRegClass() local
329 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32); in Select() local
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| D | SIInstrInfo.cpp | 1280 int RegClass = Desc.OpInfo[i].RegClass; in verifyInstruction() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1270 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1324 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local
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| D | CodeGenDAGPatterns.cpp | 1446 Record *RegClass = R->getValueAsDef("RegClass"); in getImplicitType() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1179 SDValue RegClass = CurDAG->getTargetConstant(Hexagon::DoubleRegsRegClassID, in SelectBitOp() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1696 const TargetRegisterClass *RegClass = in constrainOperandRegClass() local
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| D | ScheduleDAGRRList.cpp | 279 unsigned &RegClass, unsigned &Cost, in GetCostForDef()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2409 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { in matchRegisterByNumber()
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