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Searched defs:Regs (Results 1 – 22 of 22) sorted by relevance

/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp50 const unsigned *Regs) { in decodeRegisterClass()
188 const unsigned *Regs) { in decodeBDAddr12Operand()
198 const unsigned *Regs) { in decodeBDAddr20Operand()
208 const unsigned *Regs) { in decodeBDXAddr12Operand()
220 const unsigned *Regs) { in decodeBDXAddr20Operand()
232 const unsigned *Regs) { in decodeBDLAddr12Len8Operand()
/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h318 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated()
345 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg()
359 unsigned AllocateRegBlock(ArrayRef<uint16_t> Regs, unsigned RegsRequired) { in AllocateRegBlock()
386 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) { in AllocateReg()
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp183 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
321 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables()
444 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping()
790 const auto &Regs = RegBank.getRegisters(); in runMCDesc() local
1320 const auto &Regs = RegBank.getRegisters(); in runTargetDesc() local
1418 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc() local
DCodeGenRegisters.cpp160 RegUnitIterator(const CodeGenRegister::Vec &Regs): in RegUnitIterator()
940 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
1299 CodeGenRegister::Vec Regs; member
1328 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
2082 BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) { in computeCoveredRegisters()
DCodeGenTarget.cpp224 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); in getRegisterByName() local
DAsmMatcherEmitter.cpp2148 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterName() local
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp897 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple()
906 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple()
915 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple()
953 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off, in SelectTable() local
1116 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStore() local
1134 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStore() local
1188 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectLoadLane() local
1228 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostLoadLane() local
1283 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs); in SelectStoreLane() local
1313 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs); in SelectPostStoreLane() local
/external/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp497 const unsigned *Regs, bool IsAddress) { in parseRegister()
514 const unsigned *Regs, RegisterKind Kind) { in parseRegister()
533 const unsigned *Regs, in parseAddress()
581 SystemZAsmParser::parseAddress(OperandVector &Operands, const unsigned *Regs, in parseAddress()
/external/llvm/lib/CodeGen/AsmPrinter/
DDbgValueHistoryCalculator.cpp171 BitVector &Regs) { in collectChangingRegs()
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp194 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType()
DAggressiveAntiDepBreaker.cpp70 std::vector<unsigned> &Regs, in GetGroupRegs()
549 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
DExecutionDepsFix.cpp650 SmallVector<LiveReg, 4> Regs; in visitSoftInstr() local
DRegisterPressure.cpp424 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { in addLiveRegs()
/external/llvm/lib/Target/ARM/
DARMFrameLowering.cpp946 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local
1023 SmallVector<unsigned, 4> Regs; in emitPopInst() local
DThumb2SizeReduction.cpp215 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef() local
DARMLoadStoreOptimizer.cpp478 ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB, in MergeOps()
756 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
/external/llvm/lib/Transforms/Scalar/
DLoopStrengthReduce.cpp921 SmallPtrSetImpl<const SCEV *> &Regs, in RateRegister()
969 SmallPtrSetImpl<const SCEV *> &Regs, in RatePrimaryRegister()
986 SmallPtrSetImpl<const SCEV *> &Regs, in RateFormula()
1252 SmallPtrSet<const SCEV *, 4> Regs; member in __anon23b548b60711::LSRUse
3915 SmallPtrSet<const SCEV *, 16> Regs; in FilterOutUndesirableDedicatedRegisters() local
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp1758 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, in DecodeRegListOperand() local
1780 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; in DecodeRegListOperand16() local
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp1080 CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc, in CreateRegList()
3011 SmallVector<unsigned, 10> Regs; in parseRegisterList() local
3104 SmallVector<unsigned, 10> Regs; in parseMovePRegPair() local
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp564 SmallVector<SDValue, 4> Regs; in LowerFormalArguments() local
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp611 SmallVector<unsigned, 4> Regs; member
6194 SmallVector<unsigned, 4> Regs; in GetRegistersForValue() local
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp2684 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, in CreateRegList() argument