1 /* 2 * Copyright (c) 2013 The WebM project authors. All Rights Reserved. 3 * 4 * Use of this source code is governed by a BSD-style license 5 * that can be found in the LICENSE file in the root of the source 6 * tree. An additional intellectual property rights grant can be found 7 * in the file PATENTS. All contributing project authors may 8 * be found in the AUTHORS file in the root of the source tree. 9 */ 10 11 #ifndef VP9_COMMON_MIPS_DSPR2_VP9_LOOPFILTER_MACROS_DSPR2_H_ 12 #define VP9_COMMON_MIPS_DSPR2_VP9_LOOPFILTER_MACROS_DSPR2_H_ 13 14 #include <stdlib.h> 15 16 #include "./vpx_dsp_rtcd.h" 17 #include "vpx/vpx_integer.h" 18 #include "vpx_mem/vpx_mem.h" 19 20 #ifdef __cplusplus 21 extern "C" { 22 #endif 23 24 #if HAVE_DSPR2 25 #define STORE_F0() { \ 26 __asm__ __volatile__ ( \ 27 "sb %[q1_f0], 1(%[s4]) \n\t" \ 28 "sb %[q0_f0], 0(%[s4]) \n\t" \ 29 "sb %[p0_f0], -1(%[s4]) \n\t" \ 30 "sb %[p1_f0], -2(%[s4]) \n\t" \ 31 \ 32 : \ 33 : [q1_f0] "r" (q1_f0), [q0_f0] "r" (q0_f0), \ 34 [p0_f0] "r" (p0_f0), [p1_f0] "r" (p1_f0), \ 35 [s4] "r" (s4) \ 36 ); \ 37 \ 38 __asm__ __volatile__ ( \ 39 "srl %[q1_f0], %[q1_f0], 8 \n\t" \ 40 "srl %[q0_f0], %[q0_f0], 8 \n\t" \ 41 "srl %[p0_f0], %[p0_f0], 8 \n\t" \ 42 "srl %[p1_f0], %[p1_f0], 8 \n\t" \ 43 \ 44 : [q1_f0] "+r" (q1_f0), [q0_f0] "+r" (q0_f0), \ 45 [p0_f0] "+r" (p0_f0), [p1_f0] "+r" (p1_f0) \ 46 : \ 47 ); \ 48 \ 49 __asm__ __volatile__ ( \ 50 "sb %[q1_f0], 1(%[s3]) \n\t" \ 51 "sb %[q0_f0], 0(%[s3]) \n\t" \ 52 "sb %[p0_f0], -1(%[s3]) \n\t" \ 53 "sb %[p1_f0], -2(%[s3]) \n\t" \ 54 \ 55 : [p1_f0] "+r" (p1_f0) \ 56 : [q1_f0] "r" (q1_f0), [q0_f0] "r" (q0_f0), \ 57 [s3] "r" (s3), [p0_f0] "r" (p0_f0) \ 58 ); \ 59 \ 60 __asm__ __volatile__ ( \ 61 "srl %[q1_f0], %[q1_f0], 8 \n\t" \ 62 "srl %[q0_f0], %[q0_f0], 8 \n\t" \ 63 "srl %[p0_f0], %[p0_f0], 8 \n\t" \ 64 "srl %[p1_f0], %[p1_f0], 8 \n\t" \ 65 \ 66 : [q1_f0] "+r" (q1_f0), [q0_f0] "+r" (q0_f0), \ 67 [p0_f0] "+r" (p0_f0), [p1_f0] "+r" (p1_f0) \ 68 : \ 69 ); \ 70 \ 71 __asm__ __volatile__ ( \ 72 "sb %[q1_f0], 1(%[s2]) \n\t" \ 73 "sb %[q0_f0], 0(%[s2]) \n\t" \ 74 "sb %[p0_f0], -1(%[s2]) \n\t" \ 75 "sb %[p1_f0], -2(%[s2]) \n\t" \ 76 \ 77 : \ 78 : [q1_f0] "r" (q1_f0), [q0_f0] "r" (q0_f0), \ 79 [p0_f0] "r" (p0_f0), [p1_f0] "r" (p1_f0), \ 80 [s2] "r" (s2) \ 81 ); \ 82 \ 83 __asm__ __volatile__ ( \ 84 "srl %[q1_f0], %[q1_f0], 8 \n\t" \ 85 "srl %[q0_f0], %[q0_f0], 8 \n\t" \ 86 "srl %[p0_f0], %[p0_f0], 8 \n\t" \ 87 "srl %[p1_f0], %[p1_f0], 8 \n\t" \ 88 \ 89 : [q1_f0] "+r" (q1_f0), [q0_f0] "+r" (q0_f0), \ 90 [p0_f0] "+r" (p0_f0), [p1_f0] "+r" (p1_f0) \ 91 : \ 92 ); \ 93 \ 94 __asm__ __volatile__ ( \ 95 "sb %[q1_f0], 1(%[s1]) \n\t" \ 96 "sb %[q0_f0], 0(%[s1]) \n\t" \ 97 "sb %[p0_f0], -1(%[s1]) \n\t" \ 98 "sb %[p1_f0], -2(%[s1]) \n\t" \ 99 \ 100 : \ 101 : [q1_f0] "r" (q1_f0), [q0_f0] "r" (q0_f0), \ 102 [p0_f0] "r" (p0_f0), [p1_f0] "r" (p1_f0), \ 103 [s1] "r" (s1) \ 104 ); \ 105 } 106 107 #define STORE_F1() { \ 108 __asm__ __volatile__ ( \ 109 "sb %[q2_r], 2(%[s4]) \n\t" \ 110 "sb %[q1_r], 1(%[s4]) \n\t" \ 111 "sb %[q0_r], 0(%[s4]) \n\t" \ 112 "sb %[p0_r], -1(%[s4]) \n\t" \ 113 "sb %[p1_r], -2(%[s4]) \n\t" \ 114 "sb %[p2_r], -3(%[s4]) \n\t" \ 115 \ 116 : \ 117 : [q2_r] "r" (q2_r), [q1_r] "r" (q1_r), [q0_r] "r" (q0_r), \ 118 [p0_r] "r" (p0_r), [p1_r] "r" (p1_r), [p2_r] "r" (p2_r), \ 119 [s4] "r" (s4) \ 120 ); \ 121 \ 122 __asm__ __volatile__ ( \ 123 "srl %[q2_r], %[q2_r], 16 \n\t" \ 124 "srl %[q1_r], %[q1_r], 16 \n\t" \ 125 "srl %[q0_r], %[q0_r], 16 \n\t" \ 126 "srl %[p0_r], %[p0_r], 16 \n\t" \ 127 "srl %[p1_r], %[p1_r], 16 \n\t" \ 128 "srl %[p2_r], %[p2_r], 16 \n\t" \ 129 \ 130 : [q2_r] "+r" (q2_r), [q1_r] "+r" (q1_r), [q0_r] "+r" (q0_r), \ 131 [p0_r] "+r" (p0_r), [p1_r] "+r" (p1_r), [p2_r] "+r" (p2_r) \ 132 : \ 133 ); \ 134 \ 135 __asm__ __volatile__ ( \ 136 "sb %[q2_r], 2(%[s3]) \n\t" \ 137 "sb %[q1_r], 1(%[s3]) \n\t" \ 138 "sb %[q0_r], 0(%[s3]) \n\t" \ 139 "sb %[p0_r], -1(%[s3]) \n\t" \ 140 "sb %[p1_r], -2(%[s3]) \n\t" \ 141 "sb %[p2_r], -3(%[s3]) \n\t" \ 142 \ 143 : \ 144 : [q2_r] "r" (q2_r), [q1_r] "r" (q1_r), [q0_r] "r" (q0_r), \ 145 [p0_r] "r" (p0_r), [p1_r] "r" (p1_r), [p2_r] "r" (p2_r), \ 146 [s3] "r" (s3) \ 147 ); \ 148 \ 149 __asm__ __volatile__ ( \ 150 "sb %[q2_l], 2(%[s2]) \n\t" \ 151 "sb %[q1_l], 1(%[s2]) \n\t" \ 152 "sb %[q0_l], 0(%[s2]) \n\t" \ 153 "sb %[p0_l], -1(%[s2]) \n\t" \ 154 "sb %[p1_l], -2(%[s2]) \n\t" \ 155 "sb %[p2_l], -3(%[s2]) \n\t" \ 156 \ 157 : \ 158 : [q2_l] "r" (q2_l), [q1_l] "r" (q1_l), [q0_l] "r" (q0_l), \ 159 [p0_l] "r" (p0_l), [p1_l] "r" (p1_l), [p2_l] "r" (p2_l), \ 160 [s2] "r" (s2) \ 161 ); \ 162 \ 163 __asm__ __volatile__ ( \ 164 "srl %[q2_l], %[q2_l], 16 \n\t" \ 165 "srl %[q1_l], %[q1_l], 16 \n\t" \ 166 "srl %[q0_l], %[q0_l], 16 \n\t" \ 167 "srl %[p0_l], %[p0_l], 16 \n\t" \ 168 "srl %[p1_l], %[p1_l], 16 \n\t" \ 169 "srl %[p2_l], %[p2_l], 16 \n\t" \ 170 \ 171 : [q2_l] "+r" (q2_l), [q1_l] "+r" (q1_l), [q0_l] "+r" (q0_l), \ 172 [p0_l] "+r" (p0_l), [p1_l] "+r" (p1_l), [p2_l] "+r" (p2_l) \ 173 : \ 174 ); \ 175 \ 176 __asm__ __volatile__ ( \ 177 "sb %[q2_l], 2(%[s1]) \n\t" \ 178 "sb %[q1_l], 1(%[s1]) \n\t" \ 179 "sb %[q0_l], 0(%[s1]) \n\t" \ 180 "sb %[p0_l], -1(%[s1]) \n\t" \ 181 "sb %[p1_l], -2(%[s1]) \n\t" \ 182 "sb %[p2_l], -3(%[s1]) \n\t" \ 183 \ 184 : \ 185 : [q2_l] "r" (q2_l), [q1_l] "r" (q1_l), [q0_l] "r" (q0_l), \ 186 [p0_l] "r" (p0_l), [p1_l] "r" (p1_l), [p2_l] "r" (p2_l), \ 187 [s1] "r" (s1) \ 188 ); \ 189 } 190 191 #define STORE_F2() { \ 192 __asm__ __volatile__ ( \ 193 "sb %[q6_r], 6(%[s4]) \n\t" \ 194 "sb %[q5_r], 5(%[s4]) \n\t" \ 195 "sb %[q4_r], 4(%[s4]) \n\t" \ 196 "sb %[q3_r], 3(%[s4]) \n\t" \ 197 "sb %[q2_r], 2(%[s4]) \n\t" \ 198 "sb %[q1_r], 1(%[s4]) \n\t" \ 199 "sb %[q0_r], 0(%[s4]) \n\t" \ 200 "sb %[p0_r], -1(%[s4]) \n\t" \ 201 "sb %[p1_r], -2(%[s4]) \n\t" \ 202 "sb %[p2_r], -3(%[s4]) \n\t" \ 203 "sb %[p3_r], -4(%[s4]) \n\t" \ 204 "sb %[p4_r], -5(%[s4]) \n\t" \ 205 "sb %[p5_r], -6(%[s4]) \n\t" \ 206 "sb %[p6_r], -7(%[s4]) \n\t" \ 207 \ 208 : \ 209 : [q6_r] "r" (q6_r), [q5_r] "r" (q5_r), [q4_r] "r" (q4_r), \ 210 [q3_r] "r" (q3_r), [q2_r] "r" (q2_r), [q1_r] "r" (q1_r), \ 211 [q0_r] "r" (q0_r), \ 212 [p0_r] "r" (p0_r), [p1_r] "r" (p1_r), [p2_r] "r" (p2_r), \ 213 [p3_r] "r" (p3_r), [p4_r] "r" (p4_r), [p5_r] "r" (p5_r), \ 214 [p6_r] "r" (p6_r), \ 215 [s4] "r" (s4) \ 216 ); \ 217 \ 218 __asm__ __volatile__ ( \ 219 "srl %[q6_r], %[q6_r], 16 \n\t" \ 220 "srl %[q5_r], %[q5_r], 16 \n\t" \ 221 "srl %[q4_r], %[q4_r], 16 \n\t" \ 222 "srl %[q3_r], %[q3_r], 16 \n\t" \ 223 "srl %[q2_r], %[q2_r], 16 \n\t" \ 224 "srl %[q1_r], %[q1_r], 16 \n\t" \ 225 "srl %[q0_r], %[q0_r], 16 \n\t" \ 226 "srl %[p0_r], %[p0_r], 16 \n\t" \ 227 "srl %[p1_r], %[p1_r], 16 \n\t" \ 228 "srl %[p2_r], %[p2_r], 16 \n\t" \ 229 "srl %[p3_r], %[p3_r], 16 \n\t" \ 230 "srl %[p4_r], %[p4_r], 16 \n\t" \ 231 "srl %[p5_r], %[p5_r], 16 \n\t" \ 232 "srl %[p6_r], %[p6_r], 16 \n\t" \ 233 \ 234 : [q6_r] "+r" (q6_r), [q5_r] "+r" (q5_r), [q4_r] "+r" (q4_r), \ 235 [q3_r] "+r" (q3_r), [q2_r] "+r" (q2_r), [q1_r] "+r" (q1_r), \ 236 [q0_r] "+r" (q0_r), \ 237 [p0_r] "+r" (p0_r), [p1_r] "+r" (p1_r), [p2_r] "+r" (p2_r), \ 238 [p3_r] "+r" (p3_r), [p4_r] "+r" (p4_r), [p5_r] "+r" (p5_r), \ 239 [p6_r] "+r" (p6_r) \ 240 : \ 241 ); \ 242 \ 243 __asm__ __volatile__ ( \ 244 "sb %[q6_r], 6(%[s3]) \n\t" \ 245 "sb %[q5_r], 5(%[s3]) \n\t" \ 246 "sb %[q4_r], 4(%[s3]) \n\t" \ 247 "sb %[q3_r], 3(%[s3]) \n\t" \ 248 "sb %[q2_r], 2(%[s3]) \n\t" \ 249 "sb %[q1_r], 1(%[s3]) \n\t" \ 250 "sb %[q0_r], 0(%[s3]) \n\t" \ 251 "sb %[p0_r], -1(%[s3]) \n\t" \ 252 "sb %[p1_r], -2(%[s3]) \n\t" \ 253 "sb %[p2_r], -3(%[s3]) \n\t" \ 254 "sb %[p3_r], -4(%[s3]) \n\t" \ 255 "sb %[p4_r], -5(%[s3]) \n\t" \ 256 "sb %[p5_r], -6(%[s3]) \n\t" \ 257 "sb %[p6_r], -7(%[s3]) \n\t" \ 258 \ 259 : \ 260 : [q6_r] "r" (q6_r), [q5_r] "r" (q5_r), [q4_r] "r" (q4_r), \ 261 [q3_r] "r" (q3_r), [q2_r] "r" (q2_r), [q1_r] "r" (q1_r), \ 262 [q0_r] "r" (q0_r), \ 263 [p0_r] "r" (p0_r), [p1_r] "r" (p1_r), [p2_r] "r" (p2_r), \ 264 [p3_r] "r" (p3_r), [p4_r] "r" (p4_r), [p5_r] "r" (p5_r), \ 265 [p6_r] "r" (p6_r), \ 266 [s3] "r" (s3) \ 267 ); \ 268 \ 269 __asm__ __volatile__ ( \ 270 "sb %[q6_l], 6(%[s2]) \n\t" \ 271 "sb %[q5_l], 5(%[s2]) \n\t" \ 272 "sb %[q4_l], 4(%[s2]) \n\t" \ 273 "sb %[q3_l], 3(%[s2]) \n\t" \ 274 "sb %[q2_l], 2(%[s2]) \n\t" \ 275 "sb %[q1_l], 1(%[s2]) \n\t" \ 276 "sb %[q0_l], 0(%[s2]) \n\t" \ 277 "sb %[p0_l], -1(%[s2]) \n\t" \ 278 "sb %[p1_l], -2(%[s2]) \n\t" \ 279 "sb %[p2_l], -3(%[s2]) \n\t" \ 280 "sb %[p3_l], -4(%[s2]) \n\t" \ 281 "sb %[p4_l], -5(%[s2]) \n\t" \ 282 "sb %[p5_l], -6(%[s2]) \n\t" \ 283 "sb %[p6_l], -7(%[s2]) \n\t" \ 284 \ 285 : \ 286 : [q6_l] "r" (q6_l), [q5_l] "r" (q5_l), [q4_l] "r" (q4_l), \ 287 [q3_l] "r" (q3_l), [q2_l] "r" (q2_l), [q1_l] "r" (q1_l), \ 288 [q0_l] "r" (q0_l), \ 289 [p0_l] "r" (p0_l), [p1_l] "r" (p1_l), [p2_l] "r" (p2_l), \ 290 [p3_l] "r" (p3_l), [p4_l] "r" (p4_l), [p5_l] "r" (p5_l), \ 291 [p6_l] "r" (p6_l), \ 292 [s2] "r" (s2) \ 293 ); \ 294 \ 295 __asm__ __volatile__ ( \ 296 "srl %[q6_l], %[q6_l], 16 \n\t" \ 297 "srl %[q5_l], %[q5_l], 16 \n\t" \ 298 "srl %[q4_l], %[q4_l], 16 \n\t" \ 299 "srl %[q3_l], %[q3_l], 16 \n\t" \ 300 "srl %[q2_l], %[q2_l], 16 \n\t" \ 301 "srl %[q1_l], %[q1_l], 16 \n\t" \ 302 "srl %[q0_l], %[q0_l], 16 \n\t" \ 303 "srl %[p0_l], %[p0_l], 16 \n\t" \ 304 "srl %[p1_l], %[p1_l], 16 \n\t" \ 305 "srl %[p2_l], %[p2_l], 16 \n\t" \ 306 "srl %[p3_l], %[p3_l], 16 \n\t" \ 307 "srl %[p4_l], %[p4_l], 16 \n\t" \ 308 "srl %[p5_l], %[p5_l], 16 \n\t" \ 309 "srl %[p6_l], %[p6_l], 16 \n\t" \ 310 \ 311 : [q6_l] "+r" (q6_l), [q5_l] "+r" (q5_l), [q4_l] "+r" (q4_l), \ 312 [q3_l] "+r" (q3_l), [q2_l] "+r" (q2_l), [q1_l] "+r" (q1_l), \ 313 [q0_l] "+r" (q0_l), \ 314 [p0_l] "+r" (p0_l), [p1_l] "+r" (p1_l), [p2_l] "+r" (p2_l), \ 315 [p3_l] "+r" (p3_l), [p4_l] "+r" (p4_l), [p5_l] "+r" (p5_l), \ 316 [p6_l] "+r" (p6_l) \ 317 : \ 318 ); \ 319 \ 320 __asm__ __volatile__ ( \ 321 "sb %[q6_l], 6(%[s1]) \n\t" \ 322 "sb %[q5_l], 5(%[s1]) \n\t" \ 323 "sb %[q4_l], 4(%[s1]) \n\t" \ 324 "sb %[q3_l], 3(%[s1]) \n\t" \ 325 "sb %[q2_l], 2(%[s1]) \n\t" \ 326 "sb %[q1_l], 1(%[s1]) \n\t" \ 327 "sb %[q0_l], 0(%[s1]) \n\t" \ 328 "sb %[p0_l], -1(%[s1]) \n\t" \ 329 "sb %[p1_l], -2(%[s1]) \n\t" \ 330 "sb %[p2_l], -3(%[s1]) \n\t" \ 331 "sb %[p3_l], -4(%[s1]) \n\t" \ 332 "sb %[p4_l], -5(%[s1]) \n\t" \ 333 "sb %[p5_l], -6(%[s1]) \n\t" \ 334 "sb %[p6_l], -7(%[s1]) \n\t" \ 335 \ 336 : \ 337 : [q6_l] "r" (q6_l), [q5_l] "r" (q5_l), [q4_l] "r" (q4_l), \ 338 [q3_l] "r" (q3_l), [q2_l] "r" (q2_l), [q1_l] "r" (q1_l), \ 339 [q0_l] "r" (q0_l), \ 340 [p0_l] "r" (p0_l), [p1_l] "r" (p1_l), [p2_l] "r" (p2_l), \ 341 [p3_l] "r" (p3_l), [p4_l] "r" (p4_l), [p5_l] "r" (p5_l), \ 342 [p6_l] "r" (p6_l), \ 343 [s1] "r" (s1) \ 344 ); \ 345 } 346 347 #define PACK_LEFT_0TO3() { \ 348 __asm__ __volatile__ ( \ 349 "preceu.ph.qbl %[p3_l], %[p3] \n\t" \ 350 "preceu.ph.qbl %[p2_l], %[p2] \n\t" \ 351 "preceu.ph.qbl %[p1_l], %[p1] \n\t" \ 352 "preceu.ph.qbl %[p0_l], %[p0] \n\t" \ 353 "preceu.ph.qbl %[q0_l], %[q0] \n\t" \ 354 "preceu.ph.qbl %[q1_l], %[q1] \n\t" \ 355 "preceu.ph.qbl %[q2_l], %[q2] \n\t" \ 356 "preceu.ph.qbl %[q3_l], %[q3] \n\t" \ 357 \ 358 : [p3_l] "=&r" (p3_l), [p2_l] "=&r" (p2_l), \ 359 [p1_l] "=&r" (p1_l), [p0_l] "=&r" (p0_l), \ 360 [q0_l] "=&r" (q0_l), [q1_l] "=&r" (q1_l), \ 361 [q2_l] "=&r" (q2_l), [q3_l] "=&r" (q3_l) \ 362 : [p3] "r" (p3), [p2] "r" (p2), [p1] "r" (p1), [p0] "r" (p0), \ 363 [q0] "r" (q0), [q1] "r" (q1), [q2] "r" (q2), [q3] "r" (q3) \ 364 ); \ 365 } 366 367 #define PACK_LEFT_4TO7() { \ 368 __asm__ __volatile__ ( \ 369 "preceu.ph.qbl %[p7_l], %[p7] \n\t" \ 370 "preceu.ph.qbl %[p6_l], %[p6] \n\t" \ 371 "preceu.ph.qbl %[p5_l], %[p5] \n\t" \ 372 "preceu.ph.qbl %[p4_l], %[p4] \n\t" \ 373 "preceu.ph.qbl %[q4_l], %[q4] \n\t" \ 374 "preceu.ph.qbl %[q5_l], %[q5] \n\t" \ 375 "preceu.ph.qbl %[q6_l], %[q6] \n\t" \ 376 "preceu.ph.qbl %[q7_l], %[q7] \n\t" \ 377 \ 378 : [p7_l] "=&r" (p7_l), [p6_l] "=&r" (p6_l), \ 379 [p5_l] "=&r" (p5_l), [p4_l] "=&r" (p4_l), \ 380 [q4_l] "=&r" (q4_l), [q5_l] "=&r" (q5_l), \ 381 [q6_l] "=&r" (q6_l), [q7_l] "=&r" (q7_l) \ 382 : [p7] "r" (p7), [p6] "r" (p6), [p5] "r" (p5), [p4] "r" (p4), \ 383 [q4] "r" (q4), [q5] "r" (q5), [q6] "r" (q6), [q7] "r" (q7) \ 384 ); \ 385 } 386 387 #define PACK_RIGHT_0TO3() { \ 388 __asm__ __volatile__ ( \ 389 "preceu.ph.qbr %[p3_r], %[p3] \n\t" \ 390 "preceu.ph.qbr %[p2_r], %[p2] \n\t" \ 391 "preceu.ph.qbr %[p1_r], %[p1] \n\t" \ 392 "preceu.ph.qbr %[p0_r], %[p0] \n\t" \ 393 "preceu.ph.qbr %[q0_r], %[q0] \n\t" \ 394 "preceu.ph.qbr %[q1_r], %[q1] \n\t" \ 395 "preceu.ph.qbr %[q2_r], %[q2] \n\t" \ 396 "preceu.ph.qbr %[q3_r], %[q3] \n\t" \ 397 \ 398 : [p3_r] "=&r" (p3_r), [p2_r] "=&r" (p2_r), \ 399 [p1_r] "=&r" (p1_r), [p0_r] "=&r" (p0_r), \ 400 [q0_r] "=&r" (q0_r), [q1_r] "=&r" (q1_r), \ 401 [q2_r] "=&r" (q2_r), [q3_r] "=&r" (q3_r) \ 402 : [p3] "r" (p3), [p2] "r" (p2), [p1] "r" (p1), [p0] "r" (p0), \ 403 [q0] "r" (q0), [q1] "r" (q1), [q2] "r" (q2), [q3] "r" (q3) \ 404 ); \ 405 } 406 407 #define PACK_RIGHT_4TO7() { \ 408 __asm__ __volatile__ ( \ 409 "preceu.ph.qbr %[p7_r], %[p7] \n\t" \ 410 "preceu.ph.qbr %[p6_r], %[p6] \n\t" \ 411 "preceu.ph.qbr %[p5_r], %[p5] \n\t" \ 412 "preceu.ph.qbr %[p4_r], %[p4] \n\t" \ 413 "preceu.ph.qbr %[q4_r], %[q4] \n\t" \ 414 "preceu.ph.qbr %[q5_r], %[q5] \n\t" \ 415 "preceu.ph.qbr %[q6_r], %[q6] \n\t" \ 416 "preceu.ph.qbr %[q7_r], %[q7] \n\t" \ 417 \ 418 : [p7_r] "=&r" (p7_r), [p6_r] "=&r" (p6_r), \ 419 [p5_r] "=&r" (p5_r), [p4_r] "=&r" (p4_r), \ 420 [q4_r] "=&r" (q4_r), [q5_r] "=&r" (q5_r), \ 421 [q6_r] "=&r" (q6_r), [q7_r] "=&r" (q7_r) \ 422 : [p7] "r" (p7), [p6] "r" (p6), [p5] "r" (p5), [p4] "r" (p4), \ 423 [q4] "r" (q4), [q5] "r" (q5), [q6] "r" (q6), [q7] "r" (q7) \ 424 ); \ 425 } 426 427 #define COMBINE_LEFT_RIGHT_0TO2() { \ 428 __asm__ __volatile__ ( \ 429 "precr.qb.ph %[p2], %[p2_l], %[p2_r] \n\t" \ 430 "precr.qb.ph %[p1], %[p1_l], %[p1_r] \n\t" \ 431 "precr.qb.ph %[p0], %[p0_l], %[p0_r] \n\t" \ 432 "precr.qb.ph %[q0], %[q0_l], %[q0_r] \n\t" \ 433 "precr.qb.ph %[q1], %[q1_l], %[q1_r] \n\t" \ 434 "precr.qb.ph %[q2], %[q2_l], %[q2_r] \n\t" \ 435 \ 436 : [p2] "=&r" (p2), [p1] "=&r" (p1), [p0] "=&r" (p0), \ 437 [q0] "=&r" (q0), [q1] "=&r" (q1), [q2] "=&r" (q2) \ 438 : [p2_l] "r" (p2_l), [p2_r] "r" (p2_r), \ 439 [p1_l] "r" (p1_l), [p1_r] "r" (p1_r), \ 440 [p0_l] "r" (p0_l), [p0_r] "r" (p0_r), \ 441 [q0_l] "r" (q0_l), [q0_r] "r" (q0_r), \ 442 [q1_l] "r" (q1_l), [q1_r] "r" (q1_r), \ 443 [q2_l] "r" (q2_l), [q2_r] "r" (q2_r) \ 444 ); \ 445 } 446 447 #define COMBINE_LEFT_RIGHT_3TO6() { \ 448 __asm__ __volatile__ ( \ 449 "precr.qb.ph %[p6], %[p6_l], %[p6_r] \n\t" \ 450 "precr.qb.ph %[p5], %[p5_l], %[p5_r] \n\t" \ 451 "precr.qb.ph %[p4], %[p4_l], %[p4_r] \n\t" \ 452 "precr.qb.ph %[p3], %[p3_l], %[p3_r] \n\t" \ 453 "precr.qb.ph %[q3], %[q3_l], %[q3_r] \n\t" \ 454 "precr.qb.ph %[q4], %[q4_l], %[q4_r] \n\t" \ 455 "precr.qb.ph %[q5], %[q5_l], %[q5_r] \n\t" \ 456 "precr.qb.ph %[q6], %[q6_l], %[q6_r] \n\t" \ 457 \ 458 : [p6] "=&r" (p6),[p5] "=&r" (p5), \ 459 [p4] "=&r" (p4),[p3] "=&r" (p3), \ 460 [q3] "=&r" (q3),[q4] "=&r" (q4), \ 461 [q5] "=&r" (q5),[q6] "=&r" (q6) \ 462 : [p6_l] "r" (p6_l), [p5_l] "r" (p5_l), \ 463 [p4_l] "r" (p4_l), [p3_l] "r" (p3_l), \ 464 [p6_r] "r" (p6_r), [p5_r] "r" (p5_r), \ 465 [p4_r] "r" (p4_r), [p3_r] "r" (p3_r), \ 466 [q3_l] "r" (q3_l), [q4_l] "r" (q4_l), \ 467 [q5_l] "r" (q5_l), [q6_l] "r" (q6_l), \ 468 [q3_r] "r" (q3_r), [q4_r] "r" (q4_r), \ 469 [q5_r] "r" (q5_r), [q6_r] "r" (q6_r) \ 470 ); \ 471 } 472 473 #endif // #if HAVE_DSPR2 474 #ifdef __cplusplus 475 } // extern "C" 476 #endif 477 478 #endif // VP9_COMMON_MIPS_DSPR2_VP9_LOOPFILTER_MACROS_DSPR2_H_ 479