| /external/llvm/lib/Target/R600/ |
| D | SIMachineFunctionInfo.cpp | 40 unsigned SubIdx) { in getSpilledReg()
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| D | SILoadStoreOptimizer.cpp | 198 unsigned SubIdx) { in updateRegDefsUses()
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| D | SIInstrInfo.cpp | 418 while (unsigned SubIdx = *SubIndices++) { in copyPhysReg() local
1496 unsigned SubIdx, in buildExtractSubReg()
1525 unsigned SubIdx, in buildExtractSubRegOrImm()
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 345 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
371 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
472 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
936 unsigned SubIdx; variable
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| D | TargetInstrInfo.h | 126 unsigned &SubIdx) const { in isCoalescableExtInstr()
285 unsigned SubIdx; member
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| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, in emitLoadConstPool()
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| D | ARMBaseRegisterInfo.cpp | 394 unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
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| D | ARMBaseInstrInfo.cpp | 870 unsigned SubIdx, unsigned State, in AddDReg()
1391 unsigned DestReg, unsigned SubIdx, in reMaterialize()
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| D | ARMISelDAGToDAG.cpp | 2244 unsigned SubIdx = ARM::dsub_0; in SelectVLDDup() local
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 440 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
489 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
530 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
622 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
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| /external/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 90 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
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| D | MachineCopyPropagation.cpp | 121 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy() local
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| D | TargetInstrInfo.cpp | 286 unsigned SubIdx, unsigned &Size, in getStackSlotRange()
319 unsigned SubIdx, in reMaterialize()
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| D | RegisterCoalescer.cpp | 1127 unsigned SubIdx) { in updateRegDefsUses()
1588 const unsigned SubIdx; member in __anon6624bd4c0211::JoinVals
1743 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, unsigned LaneMask, in JoinVals()
2176 bool JoinVals::usesLanes(const MachineInstr *MI, unsigned Reg, unsigned SubIdx, in usesLanes()
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| D | MachineInstr.cpp | 69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg()
1099 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect() local
1325 unsigned SubIdx, in substituteRegister()
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| D | TwoAddressInstructionPass.cpp | 1668 unsigned SubIdx = mi->getOperand(3).getImm(); in runOnMachineFunction() local
1724 unsigned SubIdx = MI->getOperand(i+1).getImm(); in eliminateRegSequence() local
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| D | PeepholeOptimizer.cpp | 318 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
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| D | MachineVerifier.cpp | 892 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg()
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass()
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| D | CodeGenRegisters.cpp | 469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
899 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses()
1555 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1908 for (const auto &SubIdx : SubRegIndices) { in inferSubClassWithSubReg() local
1940 for (auto &SubIdx : SubRegIndices) { in inferMatchingSuperRegClass() local
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| D | AsmMatcherEmitter.cpp | 1637 int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; in buildAliasResultOperands() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 661 unsigned SubIdx; in insertSelect() local
1482 unsigned SubIdx = UseMI->getOperand(3).getSubReg(); in optimizeCompareInstr() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 521 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1492 unsigned Reg, unsigned SubIdx, in AddSubReg()
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