| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 101 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64()
110 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64()
126 unsigned &SubReg) { in getSrcFromCopy()
242 unsigned SubReg; in isProfitableToTransform() local
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| D | AArch64ISelDAGToDAG.cpp | 531 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); in narrowIfNeeded() local
691 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); in Widen() local
1041 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); in SelectIndexedLoad() local
1601 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, MVT::i32); in SelectBitfieldExtractOp() local
2163 unsigned SubReg; in Select() local
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| D | AArch64InstrInfo.cpp | 1521 int SubReg = 0, End = NumRegs, Incr = 1; in copyPhysRegTuple() local
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| D | AArch64ISelLowering.cpp | 7301 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32); in performBitcastCombine() local
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| /external/llvm/lib/CodeGen/ |
| D | LiveVariables.cpp | 198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
340 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
371 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
453 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
475 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
493 unsigned SubReg = *SubRegs; in UpdatePhysRegDefs() local
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| D | LiveRangeCalc.cpp | 65 unsigned SubReg = MO.getSubReg(); in calculate() local
158 unsigned SubReg = MO.getSubReg(); in extendToUses() local
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| D | LiveIntervalAnalysis.cpp | 513 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
946 unsigned SubReg = MO->getSubReg(); in updateAllRanges() local
1183 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1284 unsigned SubReg = MO.getSubReg(); in repairOldRegInRange() local
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| D | VirtRegMap.cpp | 261 unsigned SubReg = SR.getSubReg(); in addMBBLiveIns() local
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| D | MachineInstrBundle.cpp | 176 unsigned SubReg = *SubRegs; in finalizeBundle() local
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| D | PeepholeOptimizer.cpp | 544 bool PeepholeOptimizer::findNextSource(unsigned &Reg, unsigned &SubReg) { in findNextSource()
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| /external/llvm/lib/Target/R600/ |
| D | SIRegisterInfo.cpp | 175 unsigned SubReg = NumSubRegs > 1 ? in buildScratchLoadStore() local
216 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), in eliminateFrameIndex() local
246 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), in eliminateFrameIndex() local
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| D | SILowerControlFlow.cpp | 395 unsigned SubReg = TRI->getSubReg(Vec, AMDGPU::sub0); in IndirectSrc() local
416 unsigned SubReg = TRI->getSubReg(Dst, AMDGPU::sub0); in IndirectDst() local
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| D | R600OptimizeVectorRegisters.cpp | 192 unsigned SubReg = (*It).first; in RebuildVector() local
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| D | SIInstrInfo.cpp | 809 unsigned SubReg = Src0.getSubReg(); in commuteInstruction() local
1502 unsigned SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg() local
1537 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 843 unsigned SubReg, in shouldCoalesce()
876 unsigned SubReg; variable
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| D | TargetInstrInfo.h | 277 unsigned SubReg; member
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 109 static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) { in resultTests()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 522 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in expandExtractElementF64() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 768 unsigned SubReg, in shouldCoalesce()
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| D | ARMAsmPrinter.cpp | 368 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? in PrintAsmOperand() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 623 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); in EmitRegSequence() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 418 const CodeGenRegister *SubReg = I->second; in computeSecondarySubRegs() local
1774 CodeGenRegister *SubReg = S->second; in computeRegUnitLaneMasks() local
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