Home
last modified time | relevance | path

Searched defs:VT (Results 1 – 25 of 134) sorted by relevance

123456

/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp66 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSLDUPMask()
74 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSHDUPMask()
82 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVDDUPMask()
96 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSLLDQMask()
110 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSRLDQMask()
125 void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask()
146 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSHUFMask()
162 void DecodePSHUFHWMask(MVT VT, unsigned Imm, in DecodePSHUFHWMask()
178 void DecodePSHUFLWMask(MVT VT, unsigned Imm, in DecodePSHUFLWMask()
197 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodeSHUFPMask()
[all …]
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp92 MVT VT = Outs[i].VT; in CheckReturn() local
106 MVT VT = Outs[i].VT; in AnalyzeReturn() local
160 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
174 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
184 static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) { in isValueTypeInRegForCC()
195 MVT VT, CCAssignFn Fn) { in getRemainingRegParmsForType()
/external/llvm/include/llvm/Target/
DTargetLowering.h203 getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction()
314 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion()
364 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor()
377 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
384 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor()
391 bool isTypeLegal(EVT VT) const { in isTypeLegal()
407 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
411 void setTypeAction(MVT VT, LegalizeTypeAction Action) { in setTypeAction()
425 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { in getTypeAction()
428 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp385 MVT VT = Op.getSimpleValueType(); in Promote() local
418 EVT VT = Op.getOperand(0).getValueType(); in PromoteINT_TO_FP() local
454 EVT VT = Op.getValueType(); in PromoteFP_TO_INT() local
707 EVT VT = Op.getValueType(); in ExpandSELECT() local
761 EVT VT = Op.getValueType(); in ExpandSEXTINREG() local
784 EVT VT = Op.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
807 EVT VT = Op.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
831 EVT VT = Op.getValueType(); in ExpandZERO_EXTEND_VECTOR_INREG() local
860 EVT VT = Op.getValueType(); in ExpandBSWAP() local
891 EVT VT = Mask.getValueType(); in ExpandVSELECT() local
[all …]
DDAGCombiner.cpp431 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
769 EVT VT = N0.getValueType(); in ReassociateOps() local
890 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
981 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
1039 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
1083 EVT VT = Op.getValueType(); in PromoteExtend() local
1112 EVT VT = Op.getValueType(); in PromoteLoad() local
1578 EVT VT = N0.getValueType(); in visitADD() local
1751 EVT VT = N0.getValueType(); in visitADDC() local
1810 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT, in tryFoldToZero()
[all …]
DSelectionDAG.cpp78 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
737 EVT VT = N->getValueType(0); in VerifySDNode() local
806 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
997 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getAnyExtOrTrunc()
1003 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getSExtOrTrunc()
1009 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getZExtOrTrunc()
1015 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, in getBoolExtOrTrunc()
1024 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) { in getZeroExtendInReg()
1036 SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) { in getAnyExtendVectorInReg()
1046 SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) { in getSignExtendVectorInReg()
[all …]
DLegalizeDAG.cpp208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, in ShuffleWithNarrowerEltType()
248 EVT VT = CFP->getValueType(0); in ExpandConstantFP() local
298 EVT VT = Val.getValueType(); in ExpandUnalignedStore() local
421 EVT VT = LD->getValueType(0); in ExpandUnalignedLoad() local
581 EVT VT = Tmp1.getValueType(); in PerformInsertVectorEltInMemory() local
716 MVT VT = Value.getSimpleValueType(); in LegalizeStoreOps() local
877 MVT VT = Node->getSimpleValueType(0); in LegalizeLoadOps() local
1513 EVT VT = Node->getValueType(0); in ExpandVectorBuildThroughStack() local
1625 EVT VT = Node->getValueType(0); in ExpandDYNAMIC_STACKALLOC() local
1674 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, in LegalizeSetCCCondCode()
[all …]
DResourcePriorityQueue.cpp96 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() local
334 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
343 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() local
486 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
497 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode() local
DLegalizeFloatTypes.cpp30 static RTLIB::Libcall GetFPLibCall(EVT VT, in GetFPLibCall()
569 EVT VT = N->getValueType(0); in SoftenFloatRes_LOAD() local
622 EVT VT = N->getValueType(0); in SoftenFloatRes_VAARG() local
750 EVT VT = NewLHS.getValueType(); in SoftenFloatOp_BR_CC() local
789 EVT VT = NewLHS.getValueType(); in SoftenFloatOp_SELECT_CC() local
812 EVT VT = NewLHS.getValueType(); in SoftenFloatOp_SETCC() local
1275 EVT VT = N->getValueType(0); in ExpandFloatRes_XINT_TO_FP() local
1658 EVT VT = N->getValueType(0); in PromoteFloatOp_FP_EXTEND() local
1683 EVT VT = N->getValueType(0); in PromoteFloatOp_SETCC() local
1701 EVT VT = ST->getOperand(1)->getValueType(0); in PromoteFloatOp_STORE() local
[all …]
DLegalizeTypes.h66 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { in getTypeAction()
71 bool isTypeLegal(EVT VT) const { in isTypeLegal()
75 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) { in getEquivalentLoadRegType()
221 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
227 for (MVT VT : MVT::integer_vector_valuetypes()) { in AMDGPUTargetLowering() local
265 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering() local
314 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering() local
359 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering() local
681 EVT VT = EVT::getEVT(InitTy); in LowerConstantInitializer() local
689 EVT VT = EVT::getEVT(CFP->getType()); in LowerConstantInitializer() local
719 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy)) in LowerConstantInitializer() local
[all …]
DR600ISelLowering.cpp125 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering() local
184 for (MVT VT : ScalarIntVTs) { in R600TargetLowering() local
636 EVT VT = Op.getValueType(); in LowerOperation() local
876 EVT VT = Op.getValueType(); in ReplaceNodeResults() local
885 EVT VT = Op.getValueType(); in ReplaceNodeResults() local
894 EVT VT = Op.getValueType(); in ReplaceNodeResults() local
903 EVT VT = Op.getValueType(); in ReplaceNodeResults() local
977 EVT VT = Op.getValueType(); in LowerTrig() local
1007 EVT VT = Op.getValueType(); in LowerSHLParts() local
1043 EVT VT = Op.getValueType(); in LowerSRXParts() local
[all …]
DSIISelLowering.cpp130 for (MVT VT : MVT::integer_valuetypes()) { in SITargetLowering() local
150 for (MVT VT : MVT::integer_vector_valuetypes()) { in SITargetLowering() local
155 for (MVT VT : MVT::fp_valuetypes()) in SITargetLowering() local
297 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT, in allowsMisalignedMemoryAccesses()
371 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, in LowerParameter()
514 MVT VT = VA.getLocVT(); in LowerFormalArguments() local
847 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
966 EVT VT = Op.getOperand(3).getValueType(); in LowerINTRINSIC_VOID() local
1047 EVT VT = Op.getValueType(); in LowerFastFDIV() local
1187 EVT VT = Op.getValueType(); in LowerFDIV() local
[all …]
/external/llvm/lib/Target/X86/
DX86FastISel.cpp301 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { in isTypeLegal()
329 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, in X86FastEmitLoad()
415 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore()
476 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, in X86FastEmitStore()
930 MVT VT; in X86SelectStore() local
1086 MVT VT; in X86SelectLoad() local
1110 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { in X86ChooseCmpOpcode()
1130 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { in X86ChooseCmpImmediateOpcode()
1158 EVT VT, DebugLoc CurDbgLoc) { in X86FastEmitCompare()
1193 MVT VT; in X86SelectCmp() local
[all …]
DX86ISelLowering.cpp156 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
284 MVT VT = IntVTs[i]; in X86TargetLowering() local
466 MVT VT = IntVTs[i]; in X86TargetLowering() local
668 for (MVT VT : MVT::vector_valuetypes()) { in X86TargetLowering() local
850 MVT VT = (MVT::SimpleValueType)i; in X86TargetLowering() local
867 for (MVT VT : MVT::integer_vector_valuetypes()) { in X86TargetLowering() local
895 MVT VT = (MVT::SimpleValueType)i; in X86TargetLowering() local
932 for (MVT VT : MVT::fp_vector_valuetypes()) in X86TargetLowering() local
958 for (MVT VT : MVT::integer_vector_valuetypes()) { in X86TargetLowering() local
1073 for (MVT VT : MVT::fp_vector_valuetypes()) in X86TargetLowering() local
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp947 EVT VT = N->getValueType(0); in SelectTable() local
969 EVT VT = LD->getMemoryVT(); in SelectIndexedLoad() local
1059 EVT VT = N->getValueType(0); in SelectLoad() local
1080 EVT VT = N->getValueType(0); in SelectPostLoad() local
1112 EVT VT = N->getOperand(2)->getValueType(0); in SelectStore() local
1128 EVT VT = N->getOperand(2)->getValueType(0); in SelectPostStore() local
1156 EVT VT = V64Reg.getValueType(); in operator ()() local
1172 EVT VT = V128Reg.getValueType(); in NarrowVector() local
1184 EVT VT = N->getValueType(0); in SelectLoadLane() local
1224 EVT VT = N->getValueType(0); in SelectPostLoadLane() local
[all …]
DAArch64ISelLowering.cpp429 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
435 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering() local
587 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
621 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) { in addTypeForNEON()
690 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
695 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
731 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); in computeKnownBitsForTargetNode() local
751 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); in computeKnownBitsForTargetNode() local
1122 EVT VT = LHS.getValueType(); in emitComparison() local
1168 EVT VT = RHS.getValueType(); in getAArch64Cmp() local
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h466 bool bitsGT(MVT VT) const { in bitsGT()
471 bool bitsGE(MVT VT) const { in bitsGE()
476 bool bitsLT(MVT VT) const { in bitsLT()
481 bool bitsLE(MVT VT) const { in bitsLE()
522 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
595 SimpleValueType VT; member
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, in addTypeForNEON()
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
410 for (MVT VT : MVT::vector_valuetypes()) { in ARMTargetLowering() local
576 for (MVT VT : MVT::integer_vector_valuetypes()) { in ARMTargetLowering() local
631 for (MVT VT : MVT::fp_valuetypes()) { in ARMTargetLowering() local
642 for (MVT VT : MVT::integer_valuetypes()) in ARMTargetLowering() local
1188 EVT VT = N->getValueType(i); in getSchedulingPreference() local
3296 EVT VT = Op.getValueType(); in LowerXALUO() local
3323 EVT VT = Op.getValueType(); in LowerSELECT() local
[all …]
DARMFastISel.cpp445 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { in ARMMoveToFPReg()
455 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { in ARMMoveToIntReg()
468 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { in ARMMaterializeFP()
511 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { in ARMMaterializeInt()
581 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { in ARMMaterializeGV()
692 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
710 MVT VT; in fastMaterializeAlloca() local
734 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
746 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
862 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { in ARMSimplifyAddress()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp277 EVT VT = Op.getValueType(); in LowerOperation() local
357 SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT, in LowerImplicitParameter()
377 EVT VT = Op.getValueType(); in LowerROTL() local
390 EVT VT = Op.getValueType(); in LowerSELECT_CC() local
DAMDGPUISelLowering.cpp106 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
154 EVT VT = Op.getValueType(); in LowerIntrinsicIABS() local
167 EVT VT = Op.getValueType(); in LowerIntrinsicLRP() local
184 EVT VT = Op.getValueType(); in LowerUDIVREM() local
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp255 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) { in materializeInt()
293 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) { in materializeFP()
315 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) { in materializeGV()
348 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
454 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
466 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) { in isTypeSupported()
481 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
618 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in emitLoad()
679 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr, in emitStore()
732 MVT VT; in selectLogicalOp() local
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp260 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
274 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
401 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, in PPCSimplifyAddress()
432 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in PPCEmitLoad()
563 MVT VT; in SelectLoad() local
587 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { in PPCEmitStore()
705 MVT VT; in SelectStore() local
1037 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT, in PPCMoveToIntReg()
1866 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) { in PPCMaterializeFP()
1918 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) { in PPCMaterializeGV()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp628 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, in getIndexedAddressParts()
672 EVT VT; in getPostIndexedAddressParts() local
961 static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val) { in createSplat()
1001 EVT VT = Op.getValueType(); in LowerSETCC() local
1062 EVT VT = Op.getValueType(); in LowerLOAD() local
1171 EVT VT = Op.getValueType(); in LowerRETURNADDR() local
1193 EVT VT = Op.getValueType(); in LowerFRAMEADDR() local
1231 void HexagonTargetLowering::promoteLdStType(EVT VT, EVT PromotedLdStVT) { in promoteLdStType()
1290 MVT::SimpleValueType VT = (MVT::SimpleValueType) i; in HexagonTargetLowering() local
1612 for (MVT VT : MVT::fp_valuetypes()) in HexagonTargetLowering() local
[all …]

123456