1 //===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the PowerPC specific subclass of TargetSubtargetInfo. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H 15 #define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H 16 17 #include "PPCFrameLowering.h" 18 #include "PPCISelLowering.h" 19 #include "PPCInstrInfo.h" 20 #include "PPCSelectionDAGInfo.h" 21 #include "llvm/ADT/Triple.h" 22 #include "llvm/IR/DataLayout.h" 23 #include "llvm/MC/MCInstrItineraries.h" 24 #include "llvm/Target/TargetSubtargetInfo.h" 25 #include <string> 26 27 #define GET_SUBTARGETINFO_HEADER 28 #include "PPCGenSubtargetInfo.inc" 29 30 // GCC #defines PPC on Linux but we use it as our namespace name 31 #undef PPC 32 33 namespace llvm { 34 class StringRef; 35 36 namespace PPC { 37 // -m directive values. 38 enum { 39 DIR_NONE, 40 DIR_32, 41 DIR_440, 42 DIR_601, 43 DIR_602, 44 DIR_603, 45 DIR_7400, 46 DIR_750, 47 DIR_970, 48 DIR_A2, 49 DIR_E500mc, 50 DIR_E5500, 51 DIR_PWR3, 52 DIR_PWR4, 53 DIR_PWR5, 54 DIR_PWR5X, 55 DIR_PWR6, 56 DIR_PWR6X, 57 DIR_PWR7, 58 DIR_PWR8, 59 DIR_64 60 }; 61 } 62 63 class GlobalValue; 64 class TargetMachine; 65 66 class PPCSubtarget : public PPCGenSubtargetInfo { 67 protected: 68 /// TargetTriple - What processor and OS we're targeting. 69 Triple TargetTriple; 70 71 /// stackAlignment - The minimum alignment known to hold of the stack frame on 72 /// entry to the function and which must be maintained by every function. 73 unsigned StackAlignment; 74 75 /// Selected instruction itineraries (one entry per itinerary class.) 76 InstrItineraryData InstrItins; 77 78 /// Which cpu directive was used. 79 unsigned DarwinDirective; 80 81 /// Used by the ISel to turn in optimizations for POWER4-derived architectures 82 bool HasMFOCRF; 83 bool Has64BitSupport; 84 bool Use64BitRegs; 85 bool UseCRBits; 86 bool IsPPC64; 87 bool HasAltivec; 88 bool HasSPE; 89 bool HasQPX; 90 bool HasVSX; 91 bool HasP8Vector; 92 bool HasP8Altivec; 93 bool HasP8Crypto; 94 bool HasFCPSGN; 95 bool HasFSQRT; 96 bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; 97 bool HasRecipPrec; 98 bool HasSTFIWX; 99 bool HasLFIWAX; 100 bool HasFPRND; 101 bool HasFPCVT; 102 bool HasISEL; 103 bool HasPOPCNTD; 104 bool HasBPERMD; 105 bool HasExtDiv; 106 bool HasCMPB; 107 bool HasLDBRX; 108 bool IsBookE; 109 bool HasOnlyMSYNC; 110 bool IsE500; 111 bool IsPPC4xx; 112 bool IsPPC6xx; 113 bool DeprecatedMFTB; 114 bool DeprecatedDST; 115 bool HasLazyResolverStubs; 116 bool IsLittleEndian; 117 bool HasICBT; 118 bool HasInvariantFunctionDescriptors; 119 bool HasPartwordAtomics; 120 bool HasDirectMove; 121 bool HasHTM; 122 123 /// When targeting QPX running a stock PPC64 Linux kernel where the stack 124 /// alignment has not been changed, we need to keep the 16-byte alignment 125 /// of the stack. 126 bool IsQPXStackUnaligned; 127 128 const PPCTargetMachine &TM; 129 PPCFrameLowering FrameLowering; 130 PPCInstrInfo InstrInfo; 131 PPCTargetLowering TLInfo; 132 PPCSelectionDAGInfo TSInfo; 133 134 public: 135 /// This constructor initializes the data members to match that 136 /// of the specified triple. 137 /// 138 PPCSubtarget(const std::string &TT, const std::string &CPU, 139 const std::string &FS, const PPCTargetMachine &TM); 140 141 /// ParseSubtargetFeatures - Parses features string setting specified 142 /// subtarget options. Definition of function is auto generated by tblgen. 143 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 144 145 /// getStackAlignment - Returns the minimum alignment known to hold of the 146 /// stack frame on entry to the function and which must be maintained by every 147 /// function for this subtarget. getStackAlignment()148 unsigned getStackAlignment() const { return StackAlignment; } 149 150 /// getDarwinDirective - Returns the -m directive specified for the cpu. 151 /// getDarwinDirective()152 unsigned getDarwinDirective() const { return DarwinDirective; } 153 154 /// getInstrItins - Return the instruction itineraries based on subtarget 155 /// selection. getInstrItineraryData()156 const InstrItineraryData *getInstrItineraryData() const override { 157 return &InstrItins; 158 } 159 getFrameLowering()160 const PPCFrameLowering *getFrameLowering() const override { 161 return &FrameLowering; 162 } getInstrInfo()163 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; } getTargetLowering()164 const PPCTargetLowering *getTargetLowering() const override { 165 return &TLInfo; 166 } getSelectionDAGInfo()167 const PPCSelectionDAGInfo *getSelectionDAGInfo() const override { 168 return &TSInfo; 169 } getRegisterInfo()170 const PPCRegisterInfo *getRegisterInfo() const override { 171 return &getInstrInfo()->getRegisterInfo(); 172 } getTargetMachine()173 const PPCTargetMachine &getTargetMachine() const { return TM; } 174 175 /// initializeSubtargetDependencies - Initializes using a CPU and feature string 176 /// so that we can use initializer lists for subtarget initialization. 177 PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); 178 179 private: 180 void initializeEnvironment(); 181 void initSubtargetFeatures(StringRef CPU, StringRef FS); 182 183 public: 184 /// isPPC64 - Return true if we are generating code for 64-bit pointer mode. 185 /// 186 bool isPPC64() const; 187 188 /// has64BitSupport - Return true if the selected CPU supports 64-bit 189 /// instructions, regardless of whether we are in 32-bit or 64-bit mode. has64BitSupport()190 bool has64BitSupport() const { return Has64BitSupport; } 191 192 /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit 193 /// registers in 32-bit mode when possible. This can only true if 194 /// has64BitSupport() returns true. use64BitRegs()195 bool use64BitRegs() const { return Use64BitRegs; } 196 197 /// useCRBits - Return true if we should store and manipulate i1 values in 198 /// the individual condition register bits. useCRBits()199 bool useCRBits() const { return UseCRBits; } 200 201 /// hasLazyResolverStub - Return true if accesses to the specified global have 202 /// to go through a dyld lazy resolution stub. This means that an extra load 203 /// is required to get the address of the global. 204 bool hasLazyResolverStub(const GlobalValue *GV) const; 205 206 // isLittleEndian - True if generating little-endian code isLittleEndian()207 bool isLittleEndian() const { return IsLittleEndian; } 208 209 // Specific obvious features. hasFCPSGN()210 bool hasFCPSGN() const { return HasFCPSGN; } hasFSQRT()211 bool hasFSQRT() const { return HasFSQRT; } hasFRE()212 bool hasFRE() const { return HasFRE; } hasFRES()213 bool hasFRES() const { return HasFRES; } hasFRSQRTE()214 bool hasFRSQRTE() const { return HasFRSQRTE; } hasFRSQRTES()215 bool hasFRSQRTES() const { return HasFRSQRTES; } hasRecipPrec()216 bool hasRecipPrec() const { return HasRecipPrec; } hasSTFIWX()217 bool hasSTFIWX() const { return HasSTFIWX; } hasLFIWAX()218 bool hasLFIWAX() const { return HasLFIWAX; } hasFPRND()219 bool hasFPRND() const { return HasFPRND; } hasFPCVT()220 bool hasFPCVT() const { return HasFPCVT; } hasAltivec()221 bool hasAltivec() const { return HasAltivec; } hasSPE()222 bool hasSPE() const { return HasSPE; } hasQPX()223 bool hasQPX() const { return HasQPX; } hasVSX()224 bool hasVSX() const { return HasVSX; } hasP8Vector()225 bool hasP8Vector() const { return HasP8Vector; } hasP8Altivec()226 bool hasP8Altivec() const { return HasP8Altivec; } hasP8Crypto()227 bool hasP8Crypto() const { return HasP8Crypto; } hasMFOCRF()228 bool hasMFOCRF() const { return HasMFOCRF; } hasISEL()229 bool hasISEL() const { return HasISEL; } hasPOPCNTD()230 bool hasPOPCNTD() const { return HasPOPCNTD; } hasBPERMD()231 bool hasBPERMD() const { return HasBPERMD; } hasExtDiv()232 bool hasExtDiv() const { return HasExtDiv; } hasCMPB()233 bool hasCMPB() const { return HasCMPB; } hasLDBRX()234 bool hasLDBRX() const { return HasLDBRX; } isBookE()235 bool isBookE() const { return IsBookE; } hasOnlyMSYNC()236 bool hasOnlyMSYNC() const { return HasOnlyMSYNC; } isPPC4xx()237 bool isPPC4xx() const { return IsPPC4xx; } isPPC6xx()238 bool isPPC6xx() const { return IsPPC6xx; } isE500()239 bool isE500() const { return IsE500; } isDeprecatedMFTB()240 bool isDeprecatedMFTB() const { return DeprecatedMFTB; } isDeprecatedDST()241 bool isDeprecatedDST() const { return DeprecatedDST; } hasICBT()242 bool hasICBT() const { return HasICBT; } hasInvariantFunctionDescriptors()243 bool hasInvariantFunctionDescriptors() const { 244 return HasInvariantFunctionDescriptors; 245 } hasPartwordAtomics()246 bool hasPartwordAtomics() const { return HasPartwordAtomics; } hasDirectMove()247 bool hasDirectMove() const { return HasDirectMove; } 248 isQPXStackUnaligned()249 bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; } getPlatformStackAlignment()250 unsigned getPlatformStackAlignment() const { 251 if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned()) 252 return 32; 253 254 return 16; 255 } hasHTM()256 bool hasHTM() const { return HasHTM; } 257 getTargetTriple()258 const Triple &getTargetTriple() const { return TargetTriple; } 259 260 /// isDarwin - True if this is any darwin platform. isDarwin()261 bool isDarwin() const { return TargetTriple.isMacOSX(); } 262 /// isBGQ - True if this is a BG/Q platform. isBGQ()263 bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; } 264 isTargetELF()265 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } isTargetMachO()266 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 267 isDarwinABI()268 bool isDarwinABI() const { return isTargetMachO() || isDarwin(); } isSVR4ABI()269 bool isSVR4ABI() const { return !isDarwinABI(); } 270 bool isELFv2ABI() const; 271 enableEarlyIfConversion()272 bool enableEarlyIfConversion() const override { return hasISEL(); } 273 274 // Scheduling customization. 275 bool enableMachineScheduler() const override; 276 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 277 bool enablePostMachineScheduler() const override; 278 AntiDepBreakMode getAntiDepBreakMode() const override; 279 void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; 280 281 void overrideSchedPolicy(MachineSchedPolicy &Policy, 282 MachineInstr *begin, 283 MachineInstr *end, 284 unsigned NumRegionInstrs) const override; 285 bool useAA() const override; 286 287 bool enableSubRegLiveness() const override; 288 }; 289 } // End llvm namespace 290 291 #endif 292