Searched refs:And (Results 1 – 12 of 12) sorted by relevance
| /art/test/427-bitwise/src/ |
| D | Main.java | 45 expectEquals(1, $opt$And(5, 3)); in andInt()
46 expectEquals(0, $opt$And(0, 0)); in andInt()
47 expectEquals(0, $opt$And(0, 3)); in andInt()
48 expectEquals(0, $opt$And(3, 0)); in andInt()
49 expectEquals(1, $opt$And(1, -3)); in andInt()
50 expectEquals(-12, $opt$And(-12, -3)); in andInt()
66 expectEquals(1L, $opt$And(5L, 3L)); in andLong()
67 expectEquals(0L, $opt$And(0L, 0L)); in andLong()
68 expectEquals(0L, $opt$And(0L, 3L)); in andLong()
69 expectEquals(0L, $opt$And(3L, 0L)); in andLong()
[all …]
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| /art/tools/dexfuzz/ |
| D | README | 54 And also at least two of the following backends:
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| /art/test/800-smali/smali/ |
| D | b_22881413.smali | 133 # And somewhere at the end
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| /art/compiler/utils/mips/ |
| D | assembler_mips.h | 69 void And(Register rd, Register rs, Register rt);
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| D | assembler_mips.cc | 203 void MipsAssembler::And(Register rd, Register rs, Register rt) { in And() function in art::mips::MipsAssembler
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.h | 85 void And(GpuRegister rd, GpuRegister rs, GpuRegister rt);
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| D | assembler_mips64.cc | 210 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in And() function in art::mips64::Mips64Assembler
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| /art/compiler/utils/arm/ |
| D | assembler_arm32_test.cc | 586 TEST_F(AssemblerArm32Test, And) { in TEST_F() argument
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| /art/compiler/optimizing/ |
| D | nodes.h | 807 M(And, BinaryOperation) \
2885 DECLARE_INSTRUCTION(And);
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| D | code_generator_arm64.cc | 1214 __ And(dst, lhs, rhs); in HandleBinaryOp() local
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| D | code_generator_mips64.cc | 1074 __ And(dst, lhs, rhs_reg); in HandleBinaryOp() local
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| /art/compiler/dex/quick/x86/ |
| D | assemble_x86.cc | 127 ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,
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