| /art/runtime/arch/x86/ |
| D | context_x86.cc | 44 frame_info.CoreSpillMask() & ~(static_cast<uint32_t>(-1) << kNumberOfCpuRegisters); in FillCalleeSaves()
45 DCHECK_EQ(1, POPCOUNT(frame_info.CoreSpillMask() & ~core_regs)); // Return address spill. in FillCalleeSaves()
50 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) - 1); in FillCalleeSaves()
64 POPCOUNT(frame_info.CoreSpillMask()) - 1 + 2 * POPCOUNT(frame_info.FpSpillMask())); in FillCalleeSaves()
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| /art/runtime/arch/x86_64/ |
| D | context_x86_64.cc | 44 frame_info.CoreSpillMask() & ~(static_cast<uint32_t>(-1) << kNumberOfCpuRegisters); in FillCalleeSaves()
45 DCHECK_EQ(1, POPCOUNT(frame_info.CoreSpillMask() & ~core_regs)); // Return address spill. in FillCalleeSaves()
50 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) - 1); in FillCalleeSaves()
61 POPCOUNT(frame_info.CoreSpillMask()) - 1 + POPCOUNT(frame_info.FpSpillMask())); in FillCalleeSaves()
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| /art/runtime/arch/mips/ |
| D | context_mips.cc | 44 for (uint32_t core_reg : HighToLowBits(frame_info.CoreSpillMask())) { in FillCalleeSaves()
48 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask())); in FillCalleeSaves()
55 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) + POPCOUNT(frame_info.FpSpillMask())); in FillCalleeSaves()
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| /art/runtime/arch/arm/ |
| D | context_arm.cc | 44 uint32_t core_regs = frame_info.CoreSpillMask(); in FillCalleeSaves()
50 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask())); in FillCalleeSaves()
57 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) + POPCOUNT(frame_info.FpSpillMask())); in FillCalleeSaves()
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| /art/runtime/arch/mips64/ |
| D | context_mips64.cc | 44 for (uint32_t core_reg : HighToLowBits(frame_info.CoreSpillMask())) { in FillCalleeSaves()
48 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask())); in FillCalleeSaves()
55 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) + POPCOUNT(frame_info.FpSpillMask())); in FillCalleeSaves()
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| /art/runtime/arch/arm64/ |
| D | context_arm64.cc | 46 for (uint32_t core_reg : HighToLowBits(frame_info.CoreSpillMask())) { in FillCalleeSaves()
50 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask())); in FillCalleeSaves()
57 DCHECK_EQ(spill_pos, POPCOUNT(frame_info.CoreSpillMask()) + POPCOUNT(frame_info.FpSpillMask())); in FillCalleeSaves()
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| /art/runtime/entrypoints/quick/ |
| D | quick_trampoline_entrypoints_test.cc | 55 << type << " core spills=" << std::hex << frame_info.CoreSpillMask() << " fp spills=" in CheckFrameSize()
65 << " core spills=" << std::hex << frame_info.CoreSpillMask() in CheckPCOffset()
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| /art/runtime/quick/ |
| D | quick_method_frame_info.h | 45 uint32_t CoreSpillMask() const { in CoreSpillMask() function
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| /art/runtime/ |
| D | stack.cc | 217 uint32_t spill_mask = is_float ? frame_info.FpSpillMask() : frame_info.CoreSpillMask(); in GetVRegFromQuickCode()
224 *val = *GetVRegAddrFromQuickCode(cur_quick_frame_, code_item, frame_info.CoreSpillMask(), in GetVRegFromQuickCode()
330 uint32_t spill_mask = is_float ? frame_info.FpSpillMask() : frame_info.CoreSpillMask(); in GetVRegPairFromQuickCode()
339 cur_quick_frame_, code_item, frame_info.CoreSpillMask(), in GetVRegPairFromQuickCode()
406 uint32_t spill_mask = is_float ? frame_info.FpSpillMask() : frame_info.CoreSpillMask(); in SetVRegFromQuickCode()
414 cur_quick_frame_, code_item, frame_info.CoreSpillMask(), in SetVRegFromQuickCode()
487 uint32_t spill_mask = is_float ? frame_info.FpSpillMask() : frame_info.CoreSpillMask(); in SetVRegPairFromQuickCode()
496 cur_quick_frame_, code_item, frame_info.CoreSpillMask(), in SetVRegPairFromQuickCode()
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| D | oat_file-inl.h | 70 return reinterpret_cast<const OatQuickMethodHeader*>(code)[-1].frame_info_.CoreSpillMask(); in GetCoreSpillMask()
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| D | art_method.cc | 514 return QuickMethodFrameInfo(frame_size, callee_info.CoreSpillMask(), callee_info.FpSpillMask()); in GetQuickFrameInfo()
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.h | 64 uint32_t CoreSpillMask() const OVERRIDE;
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| D | calling_convention_mips64.cc | 139 uint32_t Mips64JniCallingConvention::CoreSpillMask() const { in CoreSpillMask() function in art::mips64::Mips64JniCallingConvention
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.h | 64 uint32_t CoreSpillMask() const OVERRIDE;
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| D | calling_convention_arm64.cc | 160 uint32_t core_spill_mask = CoreSpillMask(); in Arm64JniCallingConvention()
178 uint32_t Arm64JniCallingConvention::CoreSpillMask() const { in CoreSpillMask() function in art::arm64::Arm64JniCallingConvention
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| /art/compiler/jni/quick/x86_64/ |
| D | calling_convention_x86_64.h | 63 uint32_t CoreSpillMask() const OVERRIDE;
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| D | calling_convention_x86_64.cc | 141 uint32_t X86_64JniCallingConvention::CoreSpillMask() const { in CoreSpillMask() function in art::x86_64::X86_64JniCallingConvention
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| /art/compiler/jni/quick/x86/ |
| D | calling_convention_x86.h | 67 uint32_t CoreSpillMask() const OVERRIDE;
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| D | calling_convention_x86.cc | 177 uint32_t X86JniCallingConvention::CoreSpillMask() const { in CoreSpillMask() function in art::x86::X86JniCallingConvention
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.h | 65 uint32_t CoreSpillMask() const OVERRIDE;
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| D | calling_convention_mips.cc | 137 uint32_t MipsJniCallingConvention::CoreSpillMask() const { in CoreSpillMask() function in art::mips::MipsJniCallingConvention
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.h | 65 uint32_t CoreSpillMask() const OVERRIDE;
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| D | calling_convention_arm.cc | 239 uint32_t ArmJniCallingConvention::CoreSpillMask() const { in CoreSpillMask() function in art::arm::ArmJniCallingConvention
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| /art/runtime/arch/ |
| D | arch_test.cc | 45 << type << " core spills=" << std::hex << frame_info.CoreSpillMask() << " fp spills=" in CheckFrameSize()
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| /art/compiler/jni/quick/ |
| D | calling_convention.h | 298 virtual uint32_t CoreSpillMask() const = 0;
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