| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 643 static inline dwarf::Reg DWARFReg(CPURegister reg) { in DWARFReg() function
659 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
660 cfi_.RelOffset(DWARFReg(dst1), offset + size); in SpillRegisters()
666 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
678 cfi_.Restore(DWARFReg(dst0)); in UnspillRegisters()
679 cfi_.Restore(DWARFReg(dst1)); in UnspillRegisters()
685 cfi_.Restore(DWARFReg(dst0)); in UnspillRegisters()
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| /art/compiler/utils/arm/ |
| D | assembler_arm.cc | 373 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
377 static dwarf::Reg DWARFReg(SRegister reg) { in DWARFReg() function
402 cfi_.RelOffsetForMany(DWARFReg(Register(0)), 0, core_spill_mask, kFramePointerSize); in BuildFrame()
406 cfi_.RelOffsetForMany(DWARFReg(SRegister(0)), 0, fp_spill_mask, kFramePointerSize); in BuildFrame()
462 cfi_.RestoreMany(DWARFReg(SRegister(0)), fp_spill_mask); in RemoveFrame()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 540 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
557 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
562 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
585 cfi_.Restore(DWARFReg(reg)); in RemoveFrame()
589 cfi_.Restore(DWARFReg(RA)); in RemoveFrame()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 1065 static dwarf::Reg DWARFReg(GpuRegister reg) { in DWARFReg() function
1082 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
1087 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
1124 cfi_.Restore(DWARFReg(reg)); in RemoveFrame()
1128 cfi_.Restore(DWARFReg(RA)); in RemoveFrame()
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.cc | 2348 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
2351 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg() function
2370 cfi_.RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0); in BuildFrame()
2387 cfi_.RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset); in BuildFrame()
2428 cfi_.Restore(DWARFReg(spill.AsXmmRegister().AsFloatRegister())); in RemoveFrame()
2441 cfi_.Restore(DWARFReg(spill.AsCpuRegister().AsRegister())); in RemoveFrame()
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| /art/compiler/utils/x86/ |
| D | assembler_x86.cc | 1705 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
1723 cfi_.RelOffset(DWARFReg(spill), 0); in BuildFrame()
1764 cfi_.Restore(DWARFReg(spill)); in RemoveFrame()
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| /art/compiler/optimizing/ |
| D | code_generator_x86_64.cc | 501 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
505 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg() function
531 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
545 __ cfi().RelOffset(DWARFReg(kFpuCalleeSaves[i]), offset); in GenerateFrameEntry()
561 __ cfi().Restore(DWARFReg(kFpuCalleeSaves[i])); in GenerateFrameExit()
574 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
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| D | code_generator_arm.cc | 517 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
521 static dwarf::Reg DWARFReg(SRegister reg) { in DWARFReg() function
546 __ cfi().RelOffsetForMany(DWARFReg(R0), 0, push_mask, kArmWordSize); in GenerateFrameEntry()
551 __ cfi().RelOffsetForMany(DWARFReg(S0), 0, fpu_spill_mask_, kArmWordSize); in GenerateFrameEntry()
572 __ cfi().RestoreMany(DWARFReg(SRegister(0)), fpu_spill_mask_); in GenerateFrameExit()
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| D | code_generator_mips64.cc | 474 static dwarf::Reg DWARFReg(GpuRegister reg) { in DWARFReg() function
519 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
574 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
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| D | code_generator_x86.cc | 469 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
494 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
516 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
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