Home
last modified time | relevance | path

Searched refs:IS_QUAD_OP (Results 1 – 9 of 9) sorted by relevance

/art/compiler/dex/quick/arm64/
Dassemble_arm64.cc118 kFmtBitBlt, 23, 22, IS_QUAD_OP | REG_DEF0_USE1,
122 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
126 kFmtExtend, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
144 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
215 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
219 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
223 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
227 kFmtBitBlt, 15, 12, IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES,
239 kFmtShift, -1, -1, IS_QUAD_OP | REG_DEF0_USE12,
243 kFmtBitBlt, 15, 10, IS_QUAD_OP | REG_DEF0_USE12,
[all …]
Dutility_arm64.cc753 if (EncodingMap[opcode].flags & IS_QUAD_OP) { in OpRegRegRegShift()
927 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) in OpRegRegImm64()
1001 if (EncodingMap[opcode].flags & IS_QUAD_OP) in OpRegImm64()
/art/compiler/dex/quick/arm/
Dassemble_arm.cc578 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
583 IS_QUAD_OP | REG_DEF0_USE12 | SETS_CCODES,
588 IS_QUAD_OP | REG_DEF0_USE12 | USES_CCODES | SETS_CCODES,
611 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
615 kFmtBWidth, 4, 0, IS_QUAD_OP | REG_DEF0_USE1,
619 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD_OFF,
623 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD_OFF,
627 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD_OFF,
631 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD_OFF,
635 kFmtBitBlt, 5, 4, IS_QUAD_OP | REG_DEF0_USE12 | IS_LOAD_OFF,
[all …]
Dutility_arm.cc410 } else if (EncodingMap[opcode].flags & IS_QUAD_OP) { in OpRegRegShift()
501 if (EncodingMap[opcode].flags & IS_QUAD_OP) { in OpRegRegRegShift()
646 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP) in OpRegRegImm()
/art/compiler/dex/quick/
Dlocal_optimizations.cc40 #define LOAD_STORE_FILTER(flags) ((flags & (IS_QUAD_OP|IS_STORE)) == (IS_QUAD_OP|IS_STORE) || \
41 (flags & (IS_QUAD_OP|IS_LOAD)) == (IS_QUAD_OP|IS_LOAD) || \
Dmir_to_lir-inl.h122 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_QUAD_OP)) in NewLIR4()
Dmir_to_lir.h50 #define IS_QUAD_OP (1ULL << kIsQuadOp) macro
/art/compiler/dex/quick/x86/
Dassemble_x86.cc154 …{ kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, …
158 …{ kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, …
161 …{ kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, …
165 …{ kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W,…
168 …{ kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W,…
233 …{ kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0…
234 …{ kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0…
277 …{ kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0,…
280 …{ kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0,…
282 …{ kX86Shld64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { RE…
[all …]
/art/compiler/dex/quick/mips/
Dassemble_mips.cc151 kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
535 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | REG_USE_LR |
539 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0 | NEEDS_FIXUP,
543 kFmtUnused, -1, -1, IS_QUAD_OP | REG_DEF0_USE0 | NEEDS_FIXUP,