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Searched refs:IsPseudoLirOp (Results 1 – 14 of 14) sorted by relevance

/art/compiler/dex/quick/
Dmir_to_lir-inl.h72 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND)) in NewLIR0()
82 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_UNARY_OP)) in NewLIR1()
92 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_BINARY_OP)) in NewLIR2()
102 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_BINARY_OP)) in NewLIR2NoDest()
112 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_TERTIARY_OP)) in NewLIR3()
122 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_QUAD_OP)) in NewLIR4()
133 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_QUIN_OP)) in NewLIR5()
168 if (IsPseudoLirOp(opcode)) { in SetupResourceMasks()
Dlocal_optimizations.cc157 if (this_lir->flags.is_nop || IsPseudoLirOp(this_lir->opcode)) { in ApplyLoadStoreElimination()
211 if (check_lir->flags.is_nop || IsPseudoLirOp(check_lir->opcode)) { in ApplyLoadStoreElimination()
334 if (IsPseudoLirOp(this_lir->opcode)) { in ApplyLoadHoisting()
413 if (stop_here || !IsPseudoLirOp(check_lir->opcode)) { in ApplyLoadHoisting()
444 if (!IsPseudoLirOp(dep_lir->opcode) && in ApplyLoadHoisting()
485 bool prev_is_load = IsPseudoLirOp(prev_lir->opcode) ? false : in ApplyLoadHoisting()
Dcodegen_util.cc324 if (!lir->flags.is_nop && !IsPseudoLirOp(lir->opcode)) { in UpdateLIROffsets()
Dmir_to_lir.h581 static bool IsPseudoLirOp(int opcode) { in IsPseudoLirOp() function
/art/compiler/dex/quick/mips/
Dassemble_mips.cc790 DCHECK(!IsPseudoLirOp(lir->opcode)); in AssembleInstructions()
843 DCHECK(!IsPseudoLirOp(lir->opcode)); in AssembleInstructions()
856 DCHECK(!IsPseudoLirOp(lir->opcode)); in GetInsnSize()
Dtarget_mips.cc921 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstFlags()
926 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstName()
931 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstFmt()
/art/compiler/dex/quick/arm64/
Dassemble_arm64.cc695 if (UNLIKELY(IsPseudoLirOp(opcode))) { in EncodeLIRs()
864 (prev_lir->flags.is_nop || Mir2Lir::IsPseudoLirOp(prev_lir->opcode))) { in GetPrevEmittingLIR()
1103 DCHECK(!IsPseudoLirOp(opcode)); in GetInsnSize()
1116 if (!IsPseudoLirOp(opcode)) { in LinkFixupInsns()
Dtarget_arm64.cc800 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstFlags()
805 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstName()
810 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstFmt()
Dutility_arm64.cc95 DCHECK(!IsPseudoLirOp(opcode)); in GetLoadStoreSize()
615 DCHECK(!IsPseudoLirOp(opcode)); in OpRegRegShift()
651 DCHECK(!IsPseudoLirOp(opcode)); in OpRegRegExtend()
/art/compiler/dex/quick/arm/
Dtarget_arm.cc816 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstFlags()
821 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstName()
826 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstFmt()
Dassemble_arm.cc1091 if (IsPseudoLirOp(opcode)) { in EncodeLIRs()
1637 DCHECK(!IsPseudoLirOp(lir->opcode)); in GetInsnSize()
1649 if (!IsPseudoLirOp(lir->opcode)) { in LinkFixupInsns()
Dutility_arm.cc401 DCHECK(!IsPseudoLirOp(opcode)); in OpRegRegShift()
500 DCHECK(!IsPseudoLirOp(opcode)); in OpRegRegRegShift()
/art/compiler/dex/quick/x86/
Dtarget_x86.cc884 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstFlags()
889 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstName()
894 DCHECK(!IsPseudoLirOp(opcode)); in GetTargetInstFmt()
Dassemble_x86.cc710 DCHECK(!IsPseudoLirOp(lir->opcode)); in GetInsnSize()
1639 if (IsPseudoLirOp(lir->opcode)) { in AssembleInstructions()
1957 if (LIKELY(!IsPseudoLirOp(lir->opcode))) { in AssignInsnOffsets()