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Searched refs:S3 (Results 1 – 15 of 15) sorted by relevance

/art/compiler/jni/quick/mips64/
Dcalling_convention_mips64.cc130 callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S3)); in Mips64JniCallingConvention()
142 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA; in CoreSpillMask()
/art/runtime/arch/arm/
Dregisters_arm.h60 S3 = 3, enumerator
Dcontext_arm.cc84 fprs_[S3] = nullptr; in SmashCallerSaves()
Dquick_method_frame_info_arm.h41 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
/art/runtime/arch/mips/
Dregisters_mips.h49 S3 = 19, enumerator
Dquick_method_frame_info_mips.h29 (1 << art::mips::S2) | (1 << art::mips::S3) | (1 << art::mips::S4) | (1 << art::mips::S5) |
/art/runtime/arch/mips64/
Dregisters_mips64.h49 S3 = 19, enumerator
Dquick_method_frame_info_mips64.h29 (1 << art::mips64::S2) | (1 << art::mips64::S3) | (1 << art::mips64::S4) |
/art/runtime/arch/arm64/
Dregisters_arm64.h157 S3 = 3, enumerator
/art/compiler/optimizing/
Dcode_generator_arm.h40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
48 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 };
Dcode_generator_mips64.h59 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
/art/compiler/jni/quick/arm64/
Dcalling_convention_arm64.cc38 S0, S1, S2, S3, S4, S5, S6, S7
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc87 reg = ArmManagedRegister::FromSRegister(S3); in TEST()
94 EXPECT_EQ(S3, reg.AsSRegister()); in TEST()
147 EXPECT_EQ(S3, reg.AsOverlappingDRegisterHigh()); in TEST()
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc708 EXPECT_TRUE(vixl::s3.Is(Arm64Assembler::reg_s(S3))); in TEST()