| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 427 Jalr(ZERO, rs); in Jr()
443 CHECK_NE(rs, ZERO); in Bltc()
444 CHECK_NE(rt, ZERO); in Bltc()
450 CHECK_NE(rt, ZERO); in Bltzc()
455 CHECK_NE(rt, ZERO); in Bgtzc()
460 CHECK_NE(rs, ZERO); in Bgec()
461 CHECK_NE(rt, ZERO); in Bgec()
467 CHECK_NE(rt, ZERO); in Bgezc()
472 CHECK_NE(rt, ZERO); in Blezc()
477 CHECK_NE(rs, ZERO); in Bltuc()
[all …]
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| /art/test/055-enum-performance/src/ |
| D | SamePackagePublicEnum.java | 2 ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, enumConstant
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| D | SamePackagePrivateEnum.java | 2 ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, enumConstant
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| /art/test/055-enum-performance/src/otherpackage/ |
| D | OtherPackagePublicEnum.java | 4 ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, enumConstant
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| /art/runtime/arch/mips/ |
| D | registers_mips.cc | 31 if (rhs >= ZERO && rhs <= RA) { in operator <<()
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| D | registers_mips.h | 30 ZERO = 0, enumerator
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.cc | 32 if (rhs >= ZERO && rhs < kNumberOfGpuRegisters) { in operator <<()
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| D | registers_mips64.h | 30 ZERO = 0, enumerator
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 455 Addiu(rt, ZERO, value); in LoadImmediate()
706 Subu(dest.AsCoreRegister(), ZERO, dest.AsCoreRegister()); in LoadRef()
866 EmitBranch(in_reg.AsCoreRegister(), ZERO, &null_arg, true); in CreateHandleScopeEntry()
887 EmitBranch(scratch.AsCoreRegister(), ZERO, &null_arg, true); in CreateHandleScopeEntry()
907 EmitBranch(in_reg.AsCoreRegister(), ZERO, &null_arg, true); in LoadReferenceFromHandleScope()
963 EmitBranch(scratch.AsCoreRegister(), ZERO, slow->Entry(), false); in ExceptionPoll()
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.cc | 487 ZERO, in GenerateFrameEntry()
875 blocked_core_registers_[ZERO] = true; in SetupBlockedRegisters()
1061 GpuRegister rhs_reg = ZERO; in HandleBinaryOp()
1168 GpuRegister rhs_reg = ZERO; in HandleShift()
1736 GpuRegister rhs_reg = ZERO; in VisitCondition()
1762 __ Sltu(dst, ZERO, dst); in VisitCondition()
1977 GpuRegister rhs_reg = ZERO; in GenerateTestAndBranch()
2255 __ Move(out, ZERO); in VisitInstanceOf()
2521 __ StoreToOffset(kStoreWord, ZERO, TR, Thread::ExceptionOffset<kMips64WordSize>().Int32Value()); in VisitLoadException()
2672 __ Subu(dst, ZERO, src); in VisitNeg()
[all …]
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