/art/compiler/dex/ |
D | mir_optimization.cc | 69 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn; in DoConstantPropagation() 149 if ((mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) || in FindMoveResult() 150 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) || in FindMoveResult() 151 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_WIDE)) { in FindMoveResult() 155 if (MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) { in FindMoveResult() 189 if (static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi) { in FindPhi() 205 switch (mir->dalvikInsn.opcode) { in SelectKind() 494 Instruction::Code opcode = mir->dalvikInsn.opcode; in BasicBlockOpt() 520 mir->dalvikInsn.opcode = Instruction::GOTO; in BasicBlockOpt() 521 mir->dalvikInsn.vA = in BasicBlockOpt() [all …]
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D | mir_graph.cc | 328 int opcode = p->dalvikInsn.opcode; in FindBlock() 460 switch (insn->dalvikInsn.opcode) { in ProcessCanBranch() 464 target += insn->dalvikInsn.vA; in ProcessCanBranch() 473 target += insn->dalvikInsn.vC; in ProcessCanBranch() 482 target += insn->dalvikInsn.vB; in ProcessCanBranch() 485 LOG(FATAL) << "Unexpected opcode(" << insn->dalvikInsn.opcode << ") with kBranch set"; in ProcessCanBranch() 519 static_cast<int32_t>(insn->dalvikInsn.vB)); in ProcessCanSwitch() 535 if (insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH) { in ProcessCanSwitch() 565 (insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH) ? kPackedSwitch : kSparseSwitch; in ProcessCanSwitch() 578 (insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH) ? in ProcessCanSwitch() [all …]
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D | gvn_dead_code_elimination_test.cc | 268 mir->dalvikInsn.opcode = def->opcode; in DoPrepareMIRs() 269 mir->dalvikInsn.vB = static_cast<int32_t>(def->value); in DoPrepareMIRs() 270 mir->dalvikInsn.vB_wide = def->value; in DoPrepareMIRs() 294 mir->dalvikInsn.opcode = def->opcode; in DoPrepareMIRs() 300 mir->dalvikInsn.vA = SRegToVReg(def->defs[0], (df_attrs & DF_A_WIDE) != 0); in DoPrepareMIRs() 301 bb->data_flow_info->vreg_to_ssa_map_exit[mir->dalvikInsn.vA] = def->defs[0]; in DoPrepareMIRs() 304 bb->data_flow_info->vreg_to_ssa_map_exit[mir->dalvikInsn.vA + 1u] = def->defs[0] + 1; in DoPrepareMIRs() 310 mir->dalvikInsn.vA = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_A_WIDE) != 0); in DoPrepareMIRs() 313 mir->dalvikInsn.vB = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_B_WIDE) != 0); in DoPrepareMIRs() 316 mir->dalvikInsn.vC = SRegToVReg(mir->ssa_rep->uses, &use, (df_attrs & DF_C_WIDE) != 0); in DoPrepareMIRs() [all …]
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D | mir_analysis.cc | 973 uint32_t ending_flags = kAnalysisAttributes[ending_bb->last_mir_insn->dalvikInsn.opcode]; in AnalyzeBlock() 976 ending_flags = kAnalysisAttributes[ending_bb->last_mir_insn->dalvikInsn.opcode]; in AnalyzeBlock() 1003 if (MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) { in AnalyzeBlock() 1007 uint16_t flags = kAnalysisAttributes[mir->dalvikInsn.opcode]; in AnalyzeBlock() 1226 const bool is_iget_or_iput = IsInstructionIGetOrIPut(mir->dalvikInsn.opcode); in DoCacheFieldLoweringInfo() 1227 const bool is_iget_or_iput_quick = IsInstructionIGetQuickOrIPutQuick(mir->dalvikInsn.opcode); in DoCacheFieldLoweringInfo() 1232 field_idx = mir->dalvikInsn.vC; in DoCacheFieldLoweringInfo() 1233 access_type = IGetOrIPutMemAccessType(mir->dalvikInsn.opcode); in DoCacheFieldLoweringInfo() 1239 access_type = IGetQuickOrIPutQuickMemAccessType(mir->dalvikInsn.opcode); in DoCacheFieldLoweringInfo() 1254 } else if (IsInstructionSGetOrSPut(mir->dalvikInsn.opcode)) { in DoCacheFieldLoweringInfo() [all …]
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D | gvn_dead_code_elimination.cc | 152 DCHECK_EQ(static_cast<int>(last_data->mir->dalvikInsn.opcode), static_cast<int>(kMirOpNop)); in RemoveTrailingNops() 412 if (IsInstructionBinOp2Addr(mir->dalvikInsn.opcode) && in RenameVRegUses() 422 DCHECK_EQ(mir->dalvikInsn.v##REG, static_cast<uint32_t>(old_v_reg)); \ in RenameVRegUses() 423 mir->dalvikInsn.v##REG = new_v_reg; \ in RenameVRegUses() 439 static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi in RenameVRegUses() 509 mir->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop); in KillMIR() 515 mir->dalvikInsn.vC = mir->dalvikInsn.vB; in ChangeBinOp2AddrToPlainBinOp() 516 mir->dalvikInsn.vB = mir->dalvikInsn.vA; in ChangeBinOp2AddrToPlainBinOp() 517 mir->dalvikInsn.opcode = static_cast<Instruction::Code>( in ChangeBinOp2AddrToPlainBinOp() 518 mir->dalvikInsn.opcode - Instruction::ADD_INT_2ADDR + Instruction::ADD_INT); in ChangeBinOp2AddrToPlainBinOp() [all …]
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D | mir_dataflow.cc | 1000 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn; in FindLocalLiveIn() 1039 HandleExtended(use_v, def_v, live_in_v, mir->dalvikInsn); in FindLocalLiveIn() 1093 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn; in DataFlowSSAFormat35C() 1106 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn; in DataFlowSSAFormat3RC() 1118 const MIR::DecodedInstruction& d_insn = mir->dalvikInsn; in DataFlowSSAFormatExtended() 1126 switch (static_cast<int>(mir->dalvikInsn.opcode)) { in DataFlowSSAFormatExtended() 1181 LOG(ERROR) << "Missing case for extended MIR: " << mir->dalvikInsn.opcode; in DataFlowSSAFormatExtended() 1203 phi->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpPhi); in DoSSAConversion() 1204 phi->dalvikInsn.vA = dalvik_reg; in DoSSAConversion() 1220 if (!MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) { in DoSSAConversion() [all …]
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D | type_inference.cc | 163 DCHECK_EQ(check_cast->dalvikInsn.opcode, Instruction::CHECK_CAST); in AddCheckCast() 332 DCHECK_EQ(check_cast->dalvikInsn.opcode, Instruction::CHECK_CAST); in FindDefBlock() 425 for (; mir != main_mirs_end && static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi; in Apply() 676 if (mir->dalvikInsn.opcode == Instruction::CHECK_CAST) { in InitializeCheckCastData() 681 Type type = Type::DexType(dex_file, mir->dalvikInsn.vB); in InitializeCheckCastData() 734 uint16_t opcode = mir->dalvikInsn.opcode; in InitializeSRegs() 794 sregs_[defs[0]] = Type::DexType(cu_->dex_file, mir->dalvikInsn.vB).AsNonNull(); in InitializeSRegs() 799 sregs_[defs[0]] = Type::DexType(cu_->dex_file, mir->dalvikInsn.vC).AsNonNull(); in InitializeSRegs() 805 Type array_type = Type::DexType(cu_->dex_file, mir->dalvikInsn.vB); in InitializeSRegs() 812 DCHECK_EQ(move_result_mir->dalvikInsn.opcode, Instruction::MOVE_RESULT_OBJECT); in InitializeSRegs() [all …]
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D | post_opt_passes.cc | 35 Instruction::Code opcode = mir->dalvikInsn.opcode; in Worker()
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D | local_value_numbering.cc | 492 if ((mir->dalvikInsn.FlagsOf() & Instruction::kInvoke) != 0) { in PruneNonAliasingRefsForCatch() 1505 uint16_t opcode = mir->dalvikInsn.opcode; in GetValueNumber() 1557 if (mir->next != nullptr && mir->next->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) { in GetValueNumber() 1608 uint16_t type = mir->dalvikInsn.vC; in GetValueNumber() 1618 uint16_t type = mir->dalvikInsn.vB; in GetValueNumber() 1644 DCHECK_EQ(Low16Bits(mir->dalvikInsn.vB), mir->dalvikInsn.vB); in GetValueNumber() 1645 res = gvn_->LookupValue(Instruction::CONST_CLASS, mir->dalvikInsn.vB, 0, 0); in GetValueNumber() 1653 res = gvn_->LookupValue(Instruction::CONST_STRING, Low16Bits(mir->dalvikInsn.vB), in GetValueNumber() 1654 High16Bits(mir->dalvikInsn.vB), 0); in GetValueNumber() 1694 res = HandleConst(mir, mir->dalvikInsn.vB << 16); in GetValueNumber() [all …]
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D | type_inference_test.cc | 394 mir->dalvikInsn.opcode = def->opcode; in DoPrepareMIRs() 395 mir->dalvikInsn.vB = static_cast<int32_t>(def->value); in DoPrepareMIRs() 396 mir->dalvikInsn.vB_wide = def->value; in DoPrepareMIRs() 412 mir->dalvikInsn.vA = def->num_uses; in DoPrepareMIRs() 421 mir->dalvikInsn.vB = dex_file_builder_.GetTypeIdx(type_defs_[def->metadata].descriptor); in DoPrepareMIRs() 425 mir->dalvikInsn.vC = dex_file_builder_.GetTypeIdx(type_defs_[def->metadata].descriptor); in DoPrepareMIRs() 432 mir->dalvikInsn.opcode = def->opcode; in DoPrepareMIRs() 681 EXPECT_EQ(mirs[i].opcode, mirs_[i].dalvikInsn.opcode); in TEST_F() 736 EXPECT_EQ(mirs[i].opcode, mirs_[i].dalvikInsn.opcode); in TEST_F() 803 EXPECT_EQ(mirs[2 * i].opcode, mirs_[2 * i].dalvikInsn.opcode); in TEST_F() [all …]
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D | global_value_numbering_test.cc | 240 mir->dalvikInsn.opcode = def->opcode; in DoPrepareMIRs() 241 mir->dalvikInsn.vB = static_cast<int32_t>(def->value); in DoPrepareMIRs() 242 mir->dalvikInsn.vB_wide = def->value; in DoPrepareMIRs() 264 mir->dalvikInsn.opcode = def->opcode; in DoPrepareMIRs() 2361 mirs_[0].dalvikInsn.vC = 1234; // type for instance-of in TEST_F() 2362 mirs_[1].dalvikInsn.vC = 1234; // type for instance-of in TEST_F() 2363 mirs_[3].dalvikInsn.vB = 1234; // type for check-cast in TEST_F() 2364 mirs_[4].dalvikInsn.vB = 1234; // type for check-cast in TEST_F() 2365 mirs_[5].dalvikInsn.vB = 1234; // type for check-cast in TEST_F() 2366 mirs_[6].dalvikInsn.vB = 4321; // type for check-cast in TEST_F() [all …]
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D | mir_graph.h | 330 } dalvikInsn; variable 362 return SSARepresentation::GetStartUseIndex(dalvikInsn.opcode); in GetStartUseIndex() 472 Instruction::Code last_opcode = last_mir_insn->dalvikInsn.opcode; in BranchesToSuccessorOnlyIfNotZero() 1138 DCHECK(IsInstructionIGetOrIPut(mir->dalvikInsn.opcode)); in GetGvnIFieldId() 1145 DCHECK(IsInstructionSGetOrSPut(mir->dalvikInsn.opcode)); in GetGvnSFieldId()
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D | local_value_numbering_test.cc | 144 mir->dalvikInsn.opcode = def->opcode; in DoPrepareMIRs() 145 mir->dalvikInsn.vB = static_cast<int32_t>(def->value); in DoPrepareMIRs() 146 mir->dalvikInsn.vB_wide = def->value; in DoPrepareMIRs() 163 mir->dalvikInsn.opcode = def->opcode; in DoPrepareMIRs()
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D | global_value_numbering.cc | 110 IsInstructionReturn(bb->last_mir_insn->dalvikInsn.opcode) && in PrepareBasicBlock()
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D | mir_optimization_test.cc | 288 mir->dalvikInsn.opcode = def->opcode; in DoPrepareMIRs() 306 mir->dalvikInsn.vA = def->vA; in DoPrepareMIRs() 307 mir->dalvikInsn.vB = def->vB; in DoPrepareMIRs() 308 mir->dalvikInsn.vC = def->vC; in DoPrepareMIRs()
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/art/compiler/dex/quick/ |
D | dex_file_method_inliner.cc | 121 DCHECK_LT(arg, invoke->dalvikInsn.vA); in GetInvokeReg() 122 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); in GetInvokeReg() 123 if (IsInvokeInstructionRange(invoke->dalvikInsn.opcode)) { in GetInvokeReg() 124 return invoke->dalvikInsn.vC + arg; // Range invoke. in GetInvokeReg() 126 DCHECK_EQ(Instruction::FormatOf(invoke->dalvikInsn.opcode), Instruction::k35c); in GetInvokeReg() 127 return invoke->dalvikInsn.arg[arg]; // Non-range invoke. in GetInvokeReg() 132 DCHECK_LT(arg + 1, invoke->dalvikInsn.vA); in WideArgIsInConsecutiveDalvikRegs() 133 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); in WideArgIsInConsecutiveDalvikRegs() 134 return IsInvokeInstructionRange(invoke->dalvikInsn.opcode) || in WideArgIsInConsecutiveDalvikRegs() 135 invoke->dalvikInsn.arg[arg + 1u] == invoke->dalvikInsn.arg[arg] + 1u; in WideArgIsInConsecutiveDalvikRegs() [all …]
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D | mir_to_lir.cc | 405 DCHECK_EQ(mir->dalvikInsn.opcode, Instruction::RETURN_VOID); in GenSpecialCase() 480 const Instruction::Code opcode = mir->dalvikInsn.opcode; in CompileDalvikInstruction() 482 const uint32_t vB = mir->dalvikInsn.vB; in CompileDalvikInstruction() 483 const uint32_t vC = mir->dalvikInsn.vC; in CompileDalvikInstruction() 598 GenConstWide(rl_dest, mir->dalvikInsn.vB_wide); in CompileDalvikInstruction() 1137 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { in HandleExtendedMethodMIR() 1271 int opcode = mir->dalvikInsn.opcode; in MethodBlockCodeGen()
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D | ralloc_util.cc | 1137 int opcode = mir->dalvikInsn.opcode; in AnalyzeMIR() 1149 (opcode == Instruction::CHECK_CAST) ? mir->dalvikInsn.vB : mir->dalvikInsn.vC; in AnalyzeMIR() 1171 mir->dalvikInsn.vB)) { in AnalyzeMIR() 1173 dex_cache_array_offset = dex_cache_arrays_layout_.TypeOffset(mir->dalvikInsn.vB); in AnalyzeMIR() 1183 dex_cache_array_offset = dex_cache_arrays_layout_.StringOffset(mir->dalvikInsn.vB); in AnalyzeMIR() 1211 dex_cache_array_offset = dex_cache_arrays_layout_.MethodOffset(mir->dalvikInsn.vB); in AnalyzeMIR()
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D | quick_compiler.cc | 521 int opcode = mir->dalvikInsn.opcode; in CanCompileMethod() 527 << mir->dalvikInsn.opcode; in CanCompileMethod() 537 uint32_t invoke_method_idx = mir->dalvikInsn.vB; in CanCompileMethod()
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D | gen_common.cc | 687 DCHECK_EQ(SPutMemAccessType(mir->dalvikInsn.opcode), field_info.MemAccessType()); in GenSput() 764 DCHECK_EQ(SGetMemAccessType(mir->dalvikInsn.opcode), field_info.MemAccessType()); in GenSget() 866 auto mem_access_type = IsInstructionIGetQuickOrIPutQuick(mir->dalvikInsn.opcode) ? in GenIGet() 867 IGetQuickOrIPutQuickMemAccessType(mir->dalvikInsn.opcode) : in GenIGet() 868 IGetMemAccessType(mir->dalvikInsn.opcode); in GenIGet() 869 DCHECK_EQ(mem_access_type, field_info.MemAccessType()) << mir->dalvikInsn.opcode; in GenIGet() 945 auto mem_access_type = IsInstructionIGetQuickOrIPutQuick(mir->dalvikInsn.opcode) ? in GenIPut() 946 IGetQuickOrIPutQuickMemAccessType(mir->dalvikInsn.opcode) : in GenIPut() 947 IPutMemAccessType(mir->dalvikInsn.opcode); in GenIPut()
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/art/compiler/dex/quick/x86/ |
D | target_x86.cc | 1438 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { in GenMachineSpecificExtendedMethodMIR() 1488 GenMemBarrier(static_cast<MemBarrierKind>(mir->dalvikInsn.vA)); in GenMachineSpecificExtendedMethodMIR() 1502 for (uint32_t i = mir->dalvikInsn.vA; i <= mir->dalvikInsn.vB; i++) { in ReserveVectorRegisters() 1520 for (uint32_t i = mir->dalvikInsn.vA; i <= mir->dalvikInsn.vB; i++) { in ReturnVectorRegisters() 1537 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); in GenConst128() 1540 uint32_t *args = mir->dalvikInsn.arg; in GenConst128() 1555 constants[3] = mir->dalvikInsn.arg[0]; in AppendOpcodeWithConst() 1556 constants[2] = mir->dalvikInsn.arg[1]; in AppendOpcodeWithConst() 1557 constants[1] = mir->dalvikInsn.arg[2]; in AppendOpcodeWithConst() 1558 constants[0] = mir->dalvikInsn.arg[3]; in AppendOpcodeWithConst() [all …]
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D | quick_assemble_x86_test.cc | 203 mir->dalvikInsn.opcode = opcode; in TestVectorFn() 204 mir->dalvikInsn.vA = 0; // Destination and source. in TestVectorFn() 205 mir->dalvikInsn.vB = 1; // Source. in TestVectorFn() 208 mir->dalvikInsn.vC = (vector_type << 16) | vector_size; // Type size. in TestVectorFn()
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D | utility_x86.cc | 963 int opcode = mir->dalvikInsn.opcode; in AnalyzeMIR() 987 if (mir_graph_->GetTable(mir, mir->dalvikInsn.vB)[1] > kSmallSwitchThreshold) { in AnalyzeMIR() 1001 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in AnalyzeMIR()
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/art/compiler/dex/quick/arm/ |
D | target_arm.cc | 992 DCHECK(MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)); in GenMachineSpecificExtendedMethodMIR() 996 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { in GenMachineSpecificExtendedMethodMIR() 1012 LOG(FATAL) << "Unexpected opcode: " << mir->dalvikInsn.opcode; in GenMachineSpecificExtendedMethodMIR()
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/art/compiler/dex/quick/arm64/ |
D | target_arm64.cc | 887 DCHECK(MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)); in GenMachineSpecificExtendedMethodMIR() 891 ExtendedMIROpcode opcode = static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode); in GenMachineSpecificExtendedMethodMIR()
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