| /external/v8/src/arm64/ |
| D | constants-arm64.h | 506 ANDS = 0x60000000, enumerator
507 BICS = ANDS | NOT
521 ANDS_w_imm = LogicalImmediateFixed | ANDS,
522 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
548 ANDS_w = LogicalShiftedFixed | ANDS,
549 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
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| D | instructions-arm64.h | 238 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) { in RdMode()
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| D | macro-assembler-arm64-inl.h | 60 LogicalMacro(rd, rn, operand, ANDS); in Ands()
67 LogicalMacro(AppropriateZeroRegFor(rn), rn, operand, ANDS); in Tst()
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| D | assembler-arm64.cc | 1188 Logical(rd, rn, operand, ANDS); in ands()
2301 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd); in LogicalImmediate()
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| D | macro-assembler-arm64.cc | 96 case ANDS: // Fall through. in LogicalMacro()
114 case ANDS: // Fall through. in LogicalMacro()
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| D | simulator-arm64.cc | 1473 case ANDS: update_flags = true; // Fall through. in LogicalHelper()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-ands-bad-peephole.ll | 2 ; Check that ANDS (tst) is not merged with ADD when the immediate
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 15 ANDS r0, r2, r1 // Must be wide - 3 distinct registers
16 ANDS r2, r2, r1 // Should choose narrow
17 ANDS r2, r1, r2 // Should choose narrow - commutative
18 ANDS.W r0, r0, r1 // Explicitly wide
19 ANDS.W r3, r1, r3
21 ANDS r7, r7, r1 // Should use narrow
22 ANDS r7, r1, r7 // Commutative
23 ANDS r8, r1, r8 // high registers so must use wide encoding
24 ANDS r8, r8, r1
25 ANDS r0, r8, r0
[all …]
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| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 530 ANDS = 0x60000000, enumerator
531 BICS = ANDS | NOT
545 ANDS_w_imm = LogicalImmediateFixed | ANDS,
546 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
572 ANDS_w = LogicalShiftedFixed | ANDS,
573 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
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| D | instructions-a64.h | 305 if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) { in RdMode()
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| D | macro-assembler-a64.cc | 628 LogicalMacro(rd, rn, operand, ANDS); in Ands()
729 case ANDS: in LogicalMacro()
748 case ANDS: in LogicalMacro()
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| D | assembler-a64.cc | 966 Logical(rd, rn, operand, ANDS); in ands()
4683 Instr dest_reg = (op == ANDS) ? Rd(rd) : RdSP(rd); in LogicalImmediate()
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| D | simulator-a64.cc | 1008 case ANDS: update_flags = true; VIXL_FALLTHROUGH(); in LogicalHelper()
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| /external/llvm/test/CodeGen/ARM/ |
| D | arm-and-tst-peephole.ll | 81 ; generates a predicated ANDS instruction. Check that the predicate is printed
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 59 ANDS, enumerator
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| D | AArch64InstrInfo.td | 158 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
736 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
751 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
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| D | AArch64ISelLowering.cpp | 802 case AArch64ISD::ANDS: return "AArch64ISD::ANDS"; in getTargetNodeName()
1154 Opcode = AArch64ISD::ANDS; in emitComparison()
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| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_T2_32.c | 100 #define ANDS 0x4000 macro
757 return push_inst16(compiler, ANDS | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 85 ### ANDS ### subsection
|