Searched refs:ArgRegs (Results 1 – 7 of 7) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 200 SmallVectorImpl<unsigned> &ArgRegs,
1880 SmallVectorImpl<unsigned> &ArgRegs, in ProcessCallArgs() argument
1947 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
2211 SmallVector<unsigned, 8> ArgRegs; in ARMEmitLibcall() local
2215 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall()
2232 ArgRegs.push_back(Arg); in ARMEmitLibcall()
2240 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall()
2322 SmallVector<unsigned, 8> ArgRegs; in SelectCall() local
2327 ArgRegs.reserve(arg_size); in SelectCall()
2365 ArgRegs.push_back(Arg); in SelectCall()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 175 SmallVectorImpl<unsigned> &ArgRegs,
1243 SmallVectorImpl<unsigned> &ArgRegs, in processCallArgs() argument
1300 unsigned Arg = ArgRegs[VA.getValNo()]; in processCallArgs()
1474 SmallVector<unsigned, 8> ArgRegs; in fastLowerCall() local
1479 ArgRegs.reserve(NumArgs); in fastLowerCall()
1505 ArgRegs.push_back(Arg); in fastLowerCall()
1514 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
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| D | PPCISelLowering.cpp | 2389 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local
2393 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
2395 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
2402 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
2416 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
2421 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2423 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2427 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2428 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1371 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local
1375 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments()
1376 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments()
1380 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments()
1390 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3630 const ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local
3642 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3691 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3714 const ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs(); in writeVarArgRegs() local
3715 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs()
3726 if (ArgRegs.size() == Idx) in writeVarArgRegs()
3732 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs()
3744 for (unsigned I = Idx; I < ArgRegs.size(); in writeVarArgRegs()
3746 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 497 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local
500 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments_32()
501 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments_32()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 2845 SmallVector<unsigned, 16> ArgRegs; in fastLowerCall() local
2890 ArgRegs.push_back(ResultReg); in fastLowerCall()
2922 unsigned ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall()
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