| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 57 AssertSext, AssertZext, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
168 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
259 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc, in PromoteIntRes_BITCAST()
411 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
421 return DAG.getNode(ISD::AssertZext, dl, in PromoteIntRes_FP_TO_FP16()
1242 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
1774 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
1778 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
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| D | SelectionDAGDumper.cpp | 80 case ISD::AssertZext: return "AssertZext"; in getOperationName()
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| D | TargetLowering.cpp | 1022 case ISD::AssertZext: { in SimplifyDemandedBits()
1568 if (Op0.getOpcode() == ISD::AssertZext && in SimplifySetCC()
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| D | SelectionDAGBuilder.cpp | 754 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
4439 if (Ext.getOpcode() == ISD::AssertZext || in getTruncatedArgReg()
7392 AssertOp = ISD::AssertZext; in LowerCallTo()
7642 AssertOp = ISD::AssertZext; in LowerArguments()
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| D | SelectionDAG.cpp | 2261 case ISD::AssertZext: { in computeKnownBits()
2430 case ISD::AssertZext: in ComputeNumSignBits()
3339 case ISD::AssertZext: { in getNode()
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| D | SelectionDAGISel.cpp | 2640 case ISD::AssertZext: in SelectCodeCommon()
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| D | LegalizeDAG.cpp | 976 Result = DAG.getNode(ISD::AssertZext, dl, in LegalizeLoadOps()
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| D | DAGCombiner.cpp | 927 case ISD::AssertZext: in PromoteOperand()
928 return DAG.getNode(ISD::AssertZext, dl, PVT, in PromoteOperand()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 232 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 479 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1430 case ISD::AssertZext: in isValueExtension()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 583 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1302 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2814 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
2875 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 531 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 532 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg, in LowerFormalArguments()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3054 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
9781 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
9784 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
9787 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, in PerformCMOVCombine()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 659 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2835 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
4121 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val, in LowerCallResult()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 2365 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
10362 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, in LowerEXTRACT_VECTOR_ELT_SSE4()
10379 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, in LowerEXTRACT_VECTOR_ELT_SSE4()
10524 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, in LowerEXTRACT_VECTOR_ELT()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 8316 case ISD::AssertZext: { in checkValueWidth()
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