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Searched refs:ExtType (Results 1 – 21 of 21) sorted by relevance

/external/llvm/include/llvm/Target/
DTargetLowering.h575 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const { in getLoadExtAction() argument
579 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && in getLoadExtAction()
581 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType]; in getLoadExtAction()
585 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
587 getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
592 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
594 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
595 getLoadExtAction(ExtType, ValVT, MemVT) == Custom); in isLoadExtLegalOrCustom()
1292 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, in setLoadExtAction() argument
1294 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && in setLoadExtAction()
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/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1008 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); in printArithExtend() local
1014 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1018 ExtType == AArch64_AM::UXTX) || in printArithExtend()
1020 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
1026 O << ", " << AArch64_AM::getShiftExtendName(ExtType); in printArithExtend()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp201 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp() local
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
483 ISD::LoadExtType ExtType = LD->getExtensionType(); in ExpandLoad() local
577 switch (ExtType) { in ExpandLoad()
599 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl, in ExpandLoad()
DLegalizeVectorTypes.cpp950 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
964 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
971 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
996 ISD::LoadExtType ExtType = MLD->getExtensionType(); in SplitVecRes_MLOAD() local
1021 ExtType); in SplitVecRes_MLOAD()
1033 ExtType); in SplitVecRes_MLOAD()
2410 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD() local
2414 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
2415 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); in WidenVecRes_LOAD()
2441 ISD::LoadExtType ExtType = N->getExtensionType(); in WidenVecRes_MLOAD() local
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DLegalizeDAG.cpp875 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeLoadOps() local
876 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeLoadOps()
947 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) == in LegalizeLoadOps()
959 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
969 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
974 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
1008 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
1029 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
1060 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0), in LegalizeLoadOps()
1098 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
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DLegalizeIntegerTypes.cpp456 ISD::LoadExtType ExtType = in PromoteIntRes_LOAD() local
459 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), in PromoteIntRes_LOAD()
1899 ISD::LoadExtType ExtType = N->getExtensionType(); in ExpandIntRes_LOAD() local
1912 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
1919 if (ExtType == ISD::SEXTLOAD) { in ExpandIntRes_LOAD()
1925 } else if (ExtType == ISD::ZEXTLOAD) { in ExpandIntRes_LOAD()
1929 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); in ExpandIntRes_LOAD()
1947 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, in ExpandIntRes_LOAD()
1965 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
1993 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, in ExpandIntRes_LOAD()
DSelectionDAG.cpp253 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType() argument
254 switch (ExtType) { in getExtForLoadExtType()
2606 unsigned ExtType = LD->getExtensionType(); in ComputeNumSignBits() local
2607 switch (ExtType) { in ComputeNumSignBits()
4748 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
4777 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO); in getLoad()
4781 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
4786 ExtType = ISD::NON_EXTLOAD; in getLoad()
4787 } else if (ExtType == ISD::NON_EXTLOAD) { in getLoad()
4812 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MMO->isVolatile(), in getLoad()
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DDAGCombiner.cpp213 ISD::NodeType ExtType);
910 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteOperand() local
915 return DAG.getExtLoad(ExtType, dl, PVT, in PromoteOperand()
1132 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteLoad() local
1136 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, in PromoteLoad()
5416 ISD::NodeType ExtType) { in ExtendSetCCUses() argument
5427 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); in ExtendSetCCUses()
5476 ISD::LoadExtType ExtType = in CombineExtLoad() local
5482 while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) && in CombineExtLoad()
5488 if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT)) in CombineExtLoad()
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DLegalizeTypes.h727 LoadSDNode *LD, ISD::LoadExtType ExtType);
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h814 SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
819 SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
824 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
831 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.h132 ISD::LoadExtType ExtType,
DAMDGPUISelLowering.cpp1418 ISD::LoadExtType ExtType = Load->getExtensionType(); in LowerLOAD() local
1422 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) { in LowerLOAD()
1444 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32)) in LowerLOAD()
1463 if (ExtType == ISD::SEXTLOAD) { in LowerLOAD()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp374 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
375 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
406 if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp2180 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; in LowerFormalArguments() local
2190 ExtType = ISD::SEXTLOAD; in LowerFormalArguments()
2193 ExtType = ISD::ZEXTLOAD; in LowerFormalArguments()
2196 ExtType = ISD::EXTLOAD; in LowerFormalArguments()
2200 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN, in LowerFormalArguments()
7653 unsigned ExtType = LHS.getOpcode(); in performAddSubLongCombine() local
7662 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS); in performAddSubLongCombine()
7668 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS); in performAddSubLongCombine()
8293 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) { in checkValueWidth() argument
8294 ExtType = ISD::NON_EXTLOAD; in checkValueWidth()
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DAArch64FastISel.cpp54 AArch64_AM::ShiftExtendType ExtType; member in __anonabd4cdc40111::AArch64FastISel::Address
65 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend), in Address()
69 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; } in setExtendType()
70 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; } in getExtendType()
174 AArch64_AM::ShiftExtendType ExtType,
1350 AArch64_AM::ShiftExtendType ExtType, in emitAddSub_rx() argument
1383 .addImm(getArithExtendImm(ExtType, ShiftImm)); in emitAddSub_rx()
DAArch64ISelDAGToDAG.cpp979 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
984 if (ExtType == ISD::NON_EXTLOAD) in SelectIndexedLoad()
986 else if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
996 if (ExtType == ISD::SEXTLOAD) { in SelectIndexedLoad()
1009 if (ExtType == ISD::SEXTLOAD) { in SelectIndexedLoad()
DAArch64InstrInfo.cpp1284 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val); in isScaledAddr() local
1285 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val); in isScaledAddr()
/external/llvm/lib/Target/X86/
DX86InstrInfo.td880 ISD::LoadExtType ExtType = LD->getExtensionType();
881 if (ExtType == ISD::NON_EXTLOAD)
883 if (ExtType == ISD::EXTLOAD)
890 ISD::LoadExtType ExtType = LD->getExtensionType();
891 if (ExtType == ISD::EXTLOAD)
898 ISD::LoadExtType ExtType = LD->getExtensionType();
899 if (ExtType == ISD::NON_EXTLOAD)
901 if (ExtType == ISD::EXTLOAD)
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2151 ISD::LoadExtType ExtType = LD->getExtensionType(); in lowerLOAD() local
2161 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { in lowerLOAD()
2180 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || in lowerLOAD()
2181 (ExtType == ISD::EXTLOAD)) in lowerLOAD()
2184 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); in lowerLOAD()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp1253 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ? in adjustSubwordCmp() local
1257 Load->getExtensionType() != ExtType) in adjustSubwordCmp()
1258 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, in adjustSubwordCmp()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp4001 unsigned ExtType = in PerformANDCombine() local
4004 if (ExtType == ISD::SEXTLOAD) { in PerformANDCombine()